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get rid of even more fam10 and k8 warnings.

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Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5659 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Stefan Reinauer
2010-07-08 00:37:23 +00:00
committed by Stefan Reinauer
parent 5e33e82708
commit 817d7542f7
16 changed files with 40 additions and 53 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/cpu/amd/dualcore/dualcore_id.c
View File

@ -14,7 +14,7 @@ unsigned int read_nb_cfg_54(void)
return ( ( msr.hi >> (54-32)) & 1);
}
static inline unsigned get_initial_apicid(void)
u32 get_initial_apicid(void)
{
return ((cpuid_ebx(1) >> 24) & 0xf);
}

15
src/cpu/amd/model_10xxx/init_cpus.c
View File

@ -252,12 +252,11 @@ void wait_all_other_cores_started(u32 bsp_apicid)
printk(BIOS_DEBUG, "\n");
}
static void allow_all_aps_stop(u32 bsp_apicid)
void allow_all_aps_stop(u32 bsp_apicid)
{
/* Called by the BSP to indicate AP can stop */
/* FIXME Do APs use this?
Looks like wait_till_sysinfo_in_ram is used instead. */
/* FIXME Do APs use this? */
// allow aps to stop use 6 bits for state
lapic_write(LAPIC_MSG_REG, (bsp_apicid << 24) | 0x14);
@ -395,15 +394,11 @@ static u32 init_cpus(u32 cpu_init_detectedx)
}
#endif
/* AP is ready, Wait for the BSP to get memory configured */
/* FIXME: many cores spinning on node0 pci register seems to be bad.
* Why do we need to wait? These APs are just going to go sit in a hlt.
*/
//wait_till_sysinfo_in_ram();
/* AP is ready, configure MTRRs and go to sleep */
set_var_mtrr(0, 0x00000000, CONFIG_RAMTOP, MTRR_TYPE_WRBACK);
STOP_CAR_AND_CPU();
printk(BIOS_DEBUG,
"\nAP %02x should be halted but you are reading this....\n",
apicid);
@ -912,6 +907,7 @@ static void cpuSetAMDPCI(u8 node)
printk(BIOS_DEBUG, " done\n");
}
#ifdef UNUSED_CODE
static void cpuInitializeMCA(void)
{
/* Clears Machine Check Architecture (MCA) registers, which power on
@ -939,6 +935,7 @@ static void cpuInitializeMCA(void)
}
}
}
#endif
/**
* finalize_node_setup()

2
src/cpu/amd/model_fxx/init_cpus.c
View File

@ -191,7 +191,7 @@ void wait_all_other_cores_started(u32 bsp_apicid)
printk(BIOS_DEBUG, "\n");
}
static void allow_all_aps_stop(u32 bsp_apicid)
void allow_all_aps_stop(u32 bsp_apicid)
{
// allow aps to stop

4
src/cpu/amd/quadcore/quadcore_id.c
View File

@ -32,7 +32,7 @@ u32 read_nb_cfg_54(void)
return ( ( msr.hi >> (54-32)) & 1);
}
static u32 get_initial_apicid(void)
u32 get_initial_apicid(void)
{
return ((cpuid_ebx(1) >> 24) & 0xff);
}
@ -67,10 +67,12 @@ struct node_core_id get_node_core_id(u32 nb_cfg_54)
return id;
}
#ifdef UNUSED_CODE
static u32 get_core_num(void)
{
return (cpuid_ecx(0x80000008) & 0xff);
}
#endif
static struct node_core_id get_node_core_id_x(void)
{