intel/i945: Use romstage_handoff for S3
Don't use scratchpad registers when we have romstage_handoff to pass S3 resume flag. Scratchpad register was read too late in ramstage so acpi_is_wakeup_s3() did not evaluate correctly. This fixes low memory corruption at 0x1000-0x102c and the lack of coreboot tables (util/cbmem not working) after S3 resume. This also fixes console log from reporting early in ramstage "Normal boot" while on "S3 resume" path. Change-Id: I2922a15a90d2f8272c3482579bdd96f8f33e9705 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17675 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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@@ -375,7 +375,5 @@ int southbridge_detect_s3_resume(void);
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#define SS_CNT 0x50
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#define C3_RES 0x54
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#define SKPAD_ACPI_S3_MAGIC 0xcafed00d
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#define SKPAD_NORMAL_BOOT_MAGIC 0xcafebabe
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#endif /* __ACPI__ */
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#endif /* SOUTHBRIDGE_INTEL_I82801GX_I82801GX_H */
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@@ -19,6 +19,7 @@
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#include <device/pci.h>
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#include <console/console.h>
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#include <arch/io.h>
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#include <arch/acpi.h>
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#include <cpu/cpu.h>
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#include <cpu/x86/cache.h>
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#include <cpu/x86/smm.h>
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@@ -313,16 +314,6 @@ static void smm_relocate(void)
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static int smm_handler_copied = 0;
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static int is_wakeup(void)
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{
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device_t dev0 = dev_find_slot(0, PCI_DEVFN(0,0));
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if (!dev0)
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return 0;
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return pci_read_config32(dev0, 0xdc) == SKPAD_ACPI_S3_MAGIC;
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}
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static void smm_install(void)
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{
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/* The first CPU running this gets to copy the SMM handler. But not all
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@@ -336,7 +327,7 @@ static void smm_install(void)
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/* if we're resuming from S3, the SMM code is already in place,
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* so don't copy it again to keep the current SMM state */
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if (!is_wakeup()) {
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if (!acpi_is_wakeup_s3()) {
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/* enable the SMM memory window */
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pci_write_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), SMRAM,
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D_OPEN | G_SMRAME | C_BASE_SEG);
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