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cpu/amd/agesa: Remove leftover code

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Now that all agesa CPUs are removed this code is unused.

Change-Id: If0c082bbdb09457e3876962fa75725add11cb67c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69118
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Arthur Heymans
2022-11-01 23:33:45 +01:00
parent 0f12381083
commit 81a4fefce2
14 changed files with 16 additions and 179 deletions
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1
src/cpu/amd/Kconfig
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@@ -1,2 +1 @@
source "src/cpu/amd/agesa/Kconfig"
source "src/cpu/amd/pi/Kconfig"

1
src/cpu/amd/Makefile.inc
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@@ -1,2 +1 @@
subdirs-$(CONFIG_CPU_AMD_AGESA) += agesa
subdirs-$(CONFIG_CPU_AMD_PI) += pi

45
src/cpu/amd/agesa/Kconfig
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@@ -1,45 +0,0 @@
# SPDX-License-Identifier: GPL-2.0-only
config CPU_AMD_AGESA
bool
default n
select ARCH_X86
select DRIVERS_AMD_PI
select TSC_SYNC_LFENCE
select UDELAY_LAPIC
select LAPIC_MONOTONIC_TIMER
select SPI_FLASH if HAVE_ACPI_RESUME
select SSE2
select CACHE_MRC_SETTINGS
if CPU_AMD_AGESA
config UDELAY_LAPIC_FIXED_FSB
int
default 200
# TODO: Sync these with definitions in AGESA vendorcode.
# DCACHE_RAM_BASE must equal BSP_STACK_BASE_ADDR.
# DCACHE_RAM_SIZE must equal BSP_STACK_SIZE.
config DCACHE_RAM_BASE
hex
default 0x30000
config DCACHE_RAM_SIZE
hex
default 0x10000
config DCACHE_BSP_STACK_SIZE
hex
default 0x4000
config ENABLE_MRC_CACHE
bool "Use cached memory configuration"
default n
select SPI_FLASH
help
Try to restore memory training results
from non-volatile memory.
endif # CPU_AMD_AGESA

4
src/cpu/amd/agesa/Makefile.inc
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@@ -1,4 +0,0 @@
# SPDX-License-Identifier: GPL-2.0-only
romstage-y += ../../../soc/amd/common/block/cpu/smm/smm_helper.c
postcar-y += ../../../soc/amd/common/block/cpu/smm/smm_helper.c
ramstage-y += ../../../soc/amd/common/block/cpu/smm/smm_helper.c

2
src/cpu/amd/smm/Makefile.inc
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@@ -1,2 +0,0 @@
ramstage-y += smm_init.c

60
src/cpu/amd/smm/smm_init.c
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@@ -1,60 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <cpu/x86/msr.h>
#include <cpu/x86/mtrr.h>
#include <cpu/amd/mtrr.h>
#include <cpu/amd/msr.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/smm.h>
#include <cpu/x86/smi_deprecated.h>
#include <string.h>
void smm_init(void)
{
msr_t msr, syscfg_orig, mtrr_aseg_orig;
/* Back up MSRs for later restore */
syscfg_orig = rdmsr(SYSCFG_MSR);
mtrr_aseg_orig = rdmsr(MTRR_FIX_16K_A0000);
/* MTRR changes don't like an enabled cache */
disable_cache();
msr = syscfg_orig;
/* Allow changes to MTRR extended attributes */
msr.lo |= SYSCFG_MSR_MtrrFixDramModEn;
/* turn the extended attributes off until we fix
* them so A0000 is routed to memory
*/
msr.lo &= ~SYSCFG_MSR_MtrrFixDramEn;
wrmsr(SYSCFG_MSR, msr);
/* set DRAM access to 0xa0000 */
msr.lo = 0x18181818;
msr.hi = 0x18181818;
wrmsr(MTRR_FIX_16K_A0000, msr);
/* enable the extended features */
msr = syscfg_orig;
msr.lo |= SYSCFG_MSR_MtrrFixDramModEn;
msr.lo |= SYSCFG_MSR_MtrrFixDramEn;
wrmsr(SYSCFG_MSR, msr);
enable_cache();
/* copy the real SMM handler */
memcpy((void *)SMM_BASE, _binary_smm_start, _binary_smm_end - _binary_smm_start);
wbinvd();
disable_cache();
/* Restore SYSCFG and MTRR */
wrmsr(SYSCFG_MSR, syscfg_orig);
wrmsr(MTRR_FIX_16K_A0000, mtrr_aseg_orig);
enable_cache();
/* CPU MSR are set in CPU init */
}
void smm_init_completion(void)
{
}