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cpu/amd/agesa: Remove leftover code

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Now that all agesa CPUs are removed this code is unused.

Change-Id: If0c082bbdb09457e3876962fa75725add11cb67c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69118
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Arthur Heymans
2022-11-01 23:33:45 +01:00
parent 0f12381083
commit 81a4fefce2
14 changed files with 16 additions and 179 deletions
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2
src/arch/x86/include/arch/cpu.h
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@ -101,7 +101,7 @@ int cpu_have_cpuid(void);
static inline bool cpu_is_amd(void)
{
return CONFIG(CPU_AMD_AGESA) || CONFIG(CPU_AMD_PI) || CONFIG(SOC_AMD_COMMON);
return CONFIG(CPU_AMD_PI) || CONFIG(SOC_AMD_COMMON);
}
static inline bool cpu_is_intel(void)

1
src/cpu/amd/Kconfig
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@ -1,2 +1 @@
source "src/cpu/amd/agesa/Kconfig"
source "src/cpu/amd/pi/Kconfig"

1
src/cpu/amd/Makefile.inc
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@ -1,2 +1 @@
subdirs-$(CONFIG_CPU_AMD_AGESA) += agesa
subdirs-$(CONFIG_CPU_AMD_PI) += pi

45
src/cpu/amd/agesa/Kconfig
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@ -1,45 +0,0 @@
# SPDX-License-Identifier: GPL-2.0-only
config CPU_AMD_AGESA
bool
default n
select ARCH_X86
select DRIVERS_AMD_PI
select TSC_SYNC_LFENCE
select UDELAY_LAPIC
select LAPIC_MONOTONIC_TIMER
select SPI_FLASH if HAVE_ACPI_RESUME
select SSE2
select CACHE_MRC_SETTINGS
if CPU_AMD_AGESA
config UDELAY_LAPIC_FIXED_FSB
int
default 200
# TODO: Sync these with definitions in AGESA vendorcode.
# DCACHE_RAM_BASE must equal BSP_STACK_BASE_ADDR.
# DCACHE_RAM_SIZE must equal BSP_STACK_SIZE.
config DCACHE_RAM_BASE
hex
default 0x30000
config DCACHE_RAM_SIZE
hex
default 0x10000
config DCACHE_BSP_STACK_SIZE
hex
default 0x4000
config ENABLE_MRC_CACHE
bool "Use cached memory configuration"
default n
select SPI_FLASH
help
Try to restore memory training results
from non-volatile memory.
endif # CPU_AMD_AGESA

4
src/cpu/amd/agesa/Makefile.inc
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@ -1,4 +0,0 @@
# SPDX-License-Identifier: GPL-2.0-only
romstage-y += ../../../soc/amd/common/block/cpu/smm/smm_helper.c
postcar-y += ../../../soc/amd/common/block/cpu/smm/smm_helper.c
ramstage-y += ../../../soc/amd/common/block/cpu/smm/smm_helper.c

2
src/cpu/amd/smm/Makefile.inc
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@ -1,2 +0,0 @@
ramstage-y += smm_init.c

60
src/cpu/amd/smm/smm_init.c
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@ -1,60 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <cpu/x86/msr.h>
#include <cpu/x86/mtrr.h>
#include <cpu/amd/mtrr.h>
#include <cpu/amd/msr.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/smm.h>
#include <cpu/x86/smi_deprecated.h>
#include <string.h>
void smm_init(void)
{
msr_t msr, syscfg_orig, mtrr_aseg_orig;
/* Back up MSRs for later restore */
syscfg_orig = rdmsr(SYSCFG_MSR);
mtrr_aseg_orig = rdmsr(MTRR_FIX_16K_A0000);
/* MTRR changes don't like an enabled cache */
disable_cache();
msr = syscfg_orig;
/* Allow changes to MTRR extended attributes */
msr.lo |= SYSCFG_MSR_MtrrFixDramModEn;
/* turn the extended attributes off until we fix
* them so A0000 is routed to memory
*/
msr.lo &= ~SYSCFG_MSR_MtrrFixDramEn;
wrmsr(SYSCFG_MSR, msr);
/* set DRAM access to 0xa0000 */
msr.lo = 0x18181818;
msr.hi = 0x18181818;
wrmsr(MTRR_FIX_16K_A0000, msr);
/* enable the extended features */
msr = syscfg_orig;
msr.lo |= SYSCFG_MSR_MtrrFixDramModEn;
msr.lo |= SYSCFG_MSR_MtrrFixDramEn;
wrmsr(SYSCFG_MSR, msr);
enable_cache();
/* copy the real SMM handler */
memcpy((void *)SMM_BASE, _binary_smm_start, _binary_smm_end - _binary_smm_start);
wbinvd();
disable_cache();
/* Restore SYSCFG and MTRR */
wrmsr(SYSCFG_MSR, syscfg_orig);
wrmsr(MTRR_FIX_16K_A0000, mtrr_aseg_orig);
enable_cache();
/* CPU MSR are set in CPU init */
}
void smm_init_completion(void)
{
}

3
src/drivers/amd/agesa/Makefile.inc
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@ -21,7 +21,4 @@ ramstage-y += eventlog.c
ramstage-y += heapmanager.c
ramstage-y += acpi_tables.c
romstage-$(CONFIG_CPU_AMD_AGESA) += oem_s3.c
ramstage-$(CONFIG_CPU_AMD_AGESA) += oem_s3.c s3_mtrr.c
endif

3
src/drivers/amd/agesa/acpi_tables.c
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@ -8,8 +8,7 @@
/* Fields were removed from the structure and we cannot add them back
* without new builds of the binaryPI blobs.
*/
#if !CONFIG(CPU_AMD_AGESA_BINARY_PI) || \
CONFIG(NORTHBRIDGE_AMD_PI_00730F01)
#if CONFIG(NORTHBRIDGE_AMD_PI_00730F01)
#define HAS_ACPI_SRAT TRUE
#define HAS_ACPI_SLIT TRUE

13
src/drivers/amd/agesa/state_machine.c
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@ -14,10 +14,6 @@
#include <AMD.h>
#if CONFIG(CPU_AMD_AGESA_OPENSOURCE)
#include "Dispatcher.h"
#endif
#if ENV_RAMINIT
#include <PlatformMemoryConfiguration.h>
CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {PSO_END};
@ -25,7 +21,6 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {PSO_END};
static void agesa_locate_image(AMD_CONFIG_PARAMS *StdHeader)
{
#if CONFIG(CPU_AMD_AGESA_BINARY_PI)
const char ModuleIdentifier[] = AGESA_ID;
const void *agesa, *image;
size_t file_size;
@ -37,7 +32,6 @@ static void agesa_locate_image(AMD_CONFIG_PARAMS *StdHeader)
image = LibAmdLocateImage(agesa, agesa + file_size, 4096,
ModuleIdentifier);
StdHeader->ImageBasePtr = (void *)image;
#endif
}
void agesa_set_interface(struct sysinfo *cb)
@ -46,7 +40,6 @@ void agesa_set_interface(struct sysinfo *cb)
cb->StdHeader.CalloutPtr = GetBiosCallout;
if (CONFIG(CPU_AMD_AGESA_BINARY_PI)) {
agesa_locate_image(&cb->StdHeader);
AMD_IMAGE_HEADER *image =
(void *)(uintptr_t)cb->StdHeader.ImageBasePtr;
@ -55,21 +48,15 @@ void agesa_set_interface(struct sysinfo *cb)
(void *)(uintptr_t)image->ModuleInfoOffset;
ASSERT(module && module->ModuleDispatcher);
}
}
AGESA_STATUS module_dispatch(AGESA_STRUCT_NAME func,
AMD_CONFIG_PARAMS *StdHeader)
{
MODULE_ENTRY dispatcher;
#if CONFIG(CPU_AMD_AGESA_OPENSOURCE)
dispatcher = AmdAgesaDispatcher;
#endif
#if CONFIG(CPU_AMD_AGESA_BINARY_PI)
AMD_IMAGE_HEADER *image = (void *)(uintptr_t)StdHeader->ImageBasePtr;
AMD_MODULE_HEADER *module = (void *)(uintptr_t)image->ModuleInfoOffset;
dispatcher = module->ModuleDispatcher;
#endif
StdHeader->Func = func;
return dispatcher(StdHeader);

1
src/northbridge/amd/agesa/Kconfig
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@ -2,7 +2,6 @@
config NORTHBRIDGE_AMD_AGESA
bool
default CPU_AMD_AGESA
if NORTHBRIDGE_AMD_AGESA

34
src/vendorcode/amd/Kconfig
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@ -1,42 +1,10 @@
# SPDX-License-Identifier: GPL-2.0-only
if CPU_AMD_AGESA || CPU_AMD_PI || SOC_AMD_PI
if CPU_AMD_PI || SOC_AMD_PI
menu "AMD Platform Initialization"
choice
prompt "AGESA source"
default CPU_AMD_AGESA_BINARY_PI if CPU_AMD_PI
default CPU_AMD_AGESA_BINARY_PI if SOC_AMD_PI
default CPU_AMD_AGESA_OPENSOURCE if CPU_AMD_AGESA
help
Select the method for including the AMD Platform Initialization
code into coreboot. Platform Initialization code is required for
all AMD processors.
config CPU_AMD_AGESA_BINARY_PI
bool "binary PI"
help
Use a binary PI package. Generally, these will be stored in the
"3rdparty/blobs" directory. For some processors, these must be obtained
directly from AMD Embedded Processors Group
(http://www.amd.com/embedded).
config CPU_AMD_AGESA_OPENSOURCE
bool "open-source AGESA"
help
Build the PI package ("AGESA") from source code in the "vendorcode"
directory.
endchoice
if CPU_AMD_AGESA_OPENSOURCE
source "src/vendorcode/amd/agesa/Kconfig"
endif
if CPU_AMD_AGESA_BINARY_PI
source "src/vendorcode/amd/pi/Kconfig"
endif
config AGESA_EXTRA_TIMESTAMPS
bool "Add instrumentation for AGESA calls"

8
src/vendorcode/amd/pi/00670F00/Makefile.inc
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@ -85,7 +85,7 @@ agesa_raw_files += $(wildcard $(AGESA_ROOT)/Lib/*.[cS])
agesa_raw_files += $(wildcard $(AGESA_ROOT)/binaryPI/*.[cS])
classes-$(CONFIG_CPU_AMD_AGESA_BINARY_PI) += libagesa
classes-y += libagesa
ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32),y)
$(eval $(call create_class_compiler,libagesa,x86_32))
@ -136,7 +136,7 @@ $(AGESA_POST_MEM_ELF): $(AGESA_POST_MEM_INPUT_ELF)
$(AGESA_POST_MEM_ELF_RMOD): $(AGESA_POST_MEM_ELF)
cbfs-files-$(CONFIG_CPU_AMD_AGESA_BINARY_PI) += $(CONFIG_AGESA_PRE_MEMORY_CBFS_NAME)
cbfs-files-y += $(CONFIG_AGESA_PRE_MEMORY_CBFS_NAME)
$(CONFIG_AGESA_PRE_MEMORY_CBFS_NAME)-file := $(CONFIG_AGESA_PRE_MEMORY_BINARY_PI_FILE)
$(CONFIG_AGESA_PRE_MEMORY_CBFS_NAME)-type := stage
$(CONFIG_AGESA_PRE_MEMORY_CBFS_NAME)-options := --xip
@ -144,7 +144,7 @@ $(CONFIG_AGESA_PRE_MEMORY_CBFS_NAME)-options := --xip
# 64 byte alignment.
$(CONFIG_AGESA_PRE_MEMORY_CBFS_NAME)-align := 4096
cbfs-files-$(CONFIG_CPU_AMD_AGESA_BINARY_PI) += $(CONFIG_AGESA_POST_MEMORY_CBFS_NAME)
cbfs-files-y += $(CONFIG_AGESA_POST_MEMORY_CBFS_NAME)
$(CONFIG_AGESA_POST_MEMORY_CBFS_NAME)-file := $(AGESA_POST_MEM_ELF_RMOD)
$(CONFIG_AGESA_POST_MEMORY_CBFS_NAME)-type := stage
$(CONFIG_AGESA_POST_MEMORY_CBFS_NAME)-compression := $(CBFS_COMPRESS_FLAG)
@ -158,7 +158,7 @@ ifeq ($(AGESA_BINARYPI_INPUT_FILE),)
files_added:: warn_no_agesa
else
cbfs-files-$(CONFIG_CPU_AMD_AGESA_BINARY_PI) += $(CONFIG_AGESA_CBFS_NAME)
cbfs-files-y += $(CONFIG_AGESA_CBFS_NAME)
$(CONFIG_AGESA_CBFS_NAME)-file := $(AGESA_BINARYPI_INPUT_FILE)
ifeq ($(CONFIG_AGESA_BINARY_PI_AS_STAGE),y)

4
src/vendorcode/amd/pi/Makefile.inc
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@ -108,7 +108,7 @@ ifeq ($(CONFIG_HUDSON_IMC_FWM),y)
agesa_raw_files += $(wildcard $(src)/vendorcode/amd/pi/Lib/imc/*.c)
endif
classes-$(CONFIG_CPU_AMD_AGESA_BINARY_PI) += libagesa
classes-y += libagesa
ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32),y)
$(eval $(call create_class_compiler,libagesa,x86_32))
@ -135,7 +135,7 @@ ramstage-libs += $(agesa_output_path)/libagesa.a
#######################################################################
cbfs-files-$(CONFIG_CPU_AMD_AGESA_BINARY_PI) += $(CONFIG_AGESA_CBFS_NAME)
cbfs-files-y += $(CONFIG_AGESA_CBFS_NAME)
$(CONFIG_AGESA_CBFS_NAME)-file := $(CONFIG_AGESA_BINARY_PI_FILE)
$(CONFIG_AGESA_CBFS_NAME)-type := raw
$(CONFIG_AGESA_CBFS_NAME)-position := $(CONFIG_AGESA_BINARY_PI_LOCATION)