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soc/intel/broadwell: Enable VT-d and X2APIC

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We use the usual static addresses 0xfed90000/0xfed91000 for the GFX
IOMMU and the general IOMMU respectively. These addresses have to be
configured in MCHBAR registers and reserved from the OS.

Change-Id: I7afcce0da028a160174db2cf6b4b6735bcd59165
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/23820
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Youness Alaoui <snifikino@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit is contained in:
Matt DeVillier
2018-02-19 17:33:48 -06:00
committed by Martin Roth
parent e85e0f57ac
commit 81a6f109ba
7 changed files with 74 additions and 3 deletions
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15
src/soc/intel/broadwell/lpc.c
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@ -49,6 +49,10 @@ static void pch_enable_ioapic(struct device *dev)
{
u32 reg32;
/* Assign unique bus/dev/fn for I/O APIC */
pci_write_config16(dev, LPC_IBDF,
PCH_IOAPIC_PCI_BUS << 8 | PCH_IOAPIC_PCI_SLOT << 3);
set_ioapic_id(VIO_APIC_VADDR, 0x02);
/* affirm full set of redirection table entries ("write once") */
@ -67,6 +71,16 @@ static void pch_enable_ioapic(struct device *dev)
io_apic_write(VIO_APIC_VADDR, 0x03, 0x01);
}
static void enable_hpet(struct device *dev)
{
size_t i;
/* Assign unique bus/dev/fn for each HPET */
for (i = 0; i < 8; ++i)
pci_write_config16(dev, LPC_HnBDF(i),
PCH_HPET_PCI_BUS << 8 | PCH_HPET_PCI_SLOT << 3 | i);
}
/* PIRQ[n]_ROUT[3:0] - PIRQ Routing Control
* 0x00 - 0000 = Reserved
* 0x01 - 0001 = Reserved
@ -436,6 +450,7 @@ static void lpc_init(struct device *dev)
pch_pirq_init(dev);
setup_i8259();
i8259_configure_irq_trigger(9, 1);
enable_hpet(dev);
/* Initialize power management */
pch_power_options(dev);