sravan/system76-coreboot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

intel/i945: Call fixup_i945_errata() only for mobile version

Browse Source 
Per Mobile Intel ® 945 Express Chipset Family - Specification Update
Document Number: 309220-013 (page 15), the power saving optimization
Erratum is for Mobile Intel ® 945 Express Chipset family.

So rename 'fixup_i945_errata()' to 'fixup_i945gm_errata()' and apply
that function only for I945GM.

Change-Id: I2656021b791061b4c22c0b252656a340de76ae5e
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37188
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Elyes HAOUAS
2020-03-10 22:17:12 +01:00
committed by Patrick Georgi
parent 8355aa4de2
commit 8273e13a11
3 changed files with 4 additions and 3 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/northbridge/intel/i945/errata.c
View File

@@ -17,7 +17,7 @@
#include "i945.h" #include "i945.h"
#include "raminit.h" #include "raminit.h"
int fixup_i945_errata(void) int fixup_i945gm_errata(void)
{ {
u32 reg32; u32 reg32;

2
src/northbridge/intel/i945/raminit.h
View File

@@ -67,5 +67,5 @@ struct sys_info {
void receive_enable_adjust(struct sys_info *sysinfo); void receive_enable_adjust(struct sys_info *sysinfo);
void sdram_initialize(int boot_path, const u8 *sdram_addresses); void sdram_initialize(int boot_path, const u8 *sdram_addresses);
int fixup_i945_errata(void); int fixup_i945gm_errata(void);
#endif /* RAMINIT_H */ #endif /* RAMINIT_H */

3
src/northbridge/intel/i945/romstage.c
View File

@@ -76,7 +76,8 @@ void mainboard_romstage_entry(void)
mainboard_late_rcba_config(); mainboard_late_rcba_config();
/* Chipset Errata! */ /* Chipset Errata! */
fixup_i945_errata(); if (CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GM))
fixup_i945gm_errata();
/* Initialize the internal PCIe links before we go into stage2 */ /* Initialize the internal PCIe links before we go into stage2 */
i945_late_initialization(s3resume); i945_late_initialization(s3resume);