From 827ff248d000afebd4218041284292adf28a55f0 Mon Sep 17 00:00:00 2001 From: Tim Wawrzynczak Date: Wed, 19 May 2021 09:07:46 -0600 Subject: [PATCH] soc/intel/alderlake: Fix SA_DEVFN_CPU_PCIE6_* Change-Id: I8849f6dd2a9fdb16642de423cc82dcefd5b192ac Signed-off-by: Tim Wawrzynczak Reviewed-on: https://review.coreboot.org/c/coreboot/+/54682 Reviewed-by: Subrata Banik Reviewed-by: Furquan Shaikh Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/soc/intel/alderlake/include/soc/pci_devs.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/alderlake/include/soc/pci_devs.h b/src/soc/intel/alderlake/include/soc/pci_devs.h index af5c50e70d..f2c2fcb73e 100644 --- a/src/soc/intel/alderlake/include/soc/pci_devs.h +++ b/src/soc/intel/alderlake/include/soc/pci_devs.h @@ -41,8 +41,8 @@ #define SA_DEV_IPU PCI_DEV(0, SA_DEV_SLOT_IPU, 0) #define SA_DEV_SLOT_CPU_6 0x06 -#define SA_DEVFN_CPU_PCIE6_0 PCI_DEVFN(PCH_DEV_SLOT_CPU_6, 0) -#define SA_DEVFN_CPU_PCIE6_2 PCI_DEVFN(PCH_DEV_SLOT_CPU_6, 2) +#define SA_DEVFN_CPU_PCIE6_0 PCI_DEVFN(SA_DEV_SLOT_CPU_6, 0) +#define SA_DEVFN_CPU_PCIE6_2 PCI_DEVFN(SA_DEV_SLOT_CPU_6, 2) #define SA_DEV_SLOT_TBT 0x07 #define SA_DEVFN_TBT(x) PCI_DEVFN(SA_DEV_SLOT_TBT, (x))