sravan/system76-coreboot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

cpu/intel/haswell: Do not determine CPU type at runtime

Browse Source 
It is already known at compile-time.

Change-Id: I20303cd1f79b71268a9d734c85a1291afe9177e9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46912
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Angel Pons
2020-10-28 19:29:49 +01:00
parent 78c45bd3ef
commit 829fb2e985
2 changed files with 4 additions and 24 deletions
Download Patch File Download Diff File Expand all files Collapse all files

7
src/cpu/intel/haswell/haswell.h
View File

@@ -145,8 +145,9 @@ void set_power_limits(u8 power_limit_1_time);
int cpu_config_tdp_levels(void); int cpu_config_tdp_levels(void);
/* CPU identification */ /* CPU identification */
int haswell_family_model(void); static inline int haswell_is_ult(void)
int haswell_stepping(void); {
int haswell_is_ult(void); return CONFIG(INTEL_LYNXPOINT_LP);
}
#endif #endif

21
src/cpu/intel/haswell/haswell_init.c
View File

@@ -186,27 +186,6 @@ static const u8 power_limit_time_msr_to_sec[] = {
[0x11] = 128, [0x11] = 128,
}; };
int haswell_family_model(void)
{
return cpuid_eax(1) & 0x0fff0ff0;
}
int haswell_stepping(void)
{
return cpuid_eax(1) & 0xf;
}
/* Dynamically determine if the part is ULT. */
int haswell_is_ult(void)
{
static int ult = -1;
if (ult < 0)
ult = !!(haswell_family_model() == HASWELL_FAMILY_ULT);
return ult;
}
/* The core 100MHz BCLK is disabled in deeper c-states. One needs to calibrate /* The core 100MHz BCLK is disabled in deeper c-states. One needs to calibrate
* the 100MHz BCLK against the 24MHz BCLK to restore the clocks properly * the 100MHz BCLK against the 24MHz BCLK to restore the clocks properly
* when a core is woken up. */ * when a core is woken up. */