soc/amd/picasso/southbridge: make GPP clock outputs configurable

Make the general purpose PCIe clock outputs configurable to be either
permanently enabled, permanently disabled or dynamically enabled via
their corresponding external #CLK_REQx pins in the board's devicetree.

BUG=b:149970243
BRANCH=zork

Change-Id: I3f5760c0b869e8a9416ba9b57d182a88a2eb5e44
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44889
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

src/soc/amd/picasso/chip.h

@@ -154,6 +154,9 @@ struct soc_amd_picasso_config {
 		USB_OC_PIN_5	= 0x5,
 		USB_OC_NONE	= 0xf,
 	} usb_port_overcurrent_pin[USB_PORT_COUNT];
+
+	/* The array index is the general purpose PCIe clock output number. */
+	enum gpp_clk_req_setting gpp_clk_config[GPP_CLK_OUTPUT_COUNT];
 };
 
 typedef struct soc_amd_picasso_config config_t;