From 82bca31f3fa197818f262a118cbd7babf4e240b3 Mon Sep 17 00:00:00 2001
From: Jeremy Soller <jeremy@system76.com>
Date: Tue, 10 Nov 2020 14:26:37 -0700
Subject: [PATCH] Disable CPU PCIE RP AER by default

Change-Id: I619e7845d16eeca5544cd88789facebe18742c46
---
 src/soc/intel/tigerlake/fsp_params.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c
index cf51542560..493a466dc8 100644
--- a/src/soc/intel/tigerlake/fsp_params.c
+++ b/src/soc/intel/tigerlake/fsp_params.c
@@ -192,6 +192,11 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
 	memcpy(params->PcieRpClkReqDetect, config->PcieRpClkReqDetect,
 		sizeof(config->PcieRpClkReqDetect));
 
+	/* TODO: CPU RP Configs */
+	for (i = 0; i < 4; i++) {
+		params->CpuPcieRpAdvancedErrorReporting[i] = 0;
+	}
+
 	/* Enable xDCI controller if enabled in devicetree and allowed */
 	dev = pcidev_path_on_root(PCH_DEVFN_USBOTG);
 	if (dev) {