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AMD Bettong: refactor PCI interrupt table

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1. Use write_pci_int_table to write registers 0xC00/0xC01.
2. Add GPIO, I2C and UART interrupt according
"BKDG for AMD Family 15h Models 60h-6Fh Processors",
50742 Rev 3.01 - July 17, 2015
3. The interrupt valudes are moved from bettong/mptable.c.
All devices work in Windows 10.

Change-Id: Iad13bc02c84a5dfc7c24356436ac560f593304d7
Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com>
Reviewed-on: http://review.coreboot.org/11746
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
This commit is contained in:
WANG Siyuan
2015-08-18 06:22:22 +08:00
committed by Zheng Bao
parent 1bb4083859
commit 839d68f101
4 changed files with 84 additions and 43 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
src/southbridge/amd/pi/hudson/amd_pci_int_defs.h
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@@ -77,8 +77,14 @@
#endif
#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_KERN)
#define FCH_INT_TABLE_SIZE 0x75
#define FCH_INT_TABLE_SIZE 0x76
#define PIRQ_GPIO 0x62 /* GPIO Controller Interrupt */
#define PIRQ_I2C0 0x70
#define PIRQ_I2C1 0x71
#define PIRQ_I2C2 0x72
#define PIRQ_I2C3 0x73
#define PIRQ_UART0 0x74
#define PIRQ_UART1 0x75
#endif
#endif /* AMD_PCI_INT_DEFS_H */

3
src/southbridge/amd/pi/hudson/amd_pci_int_types.h
View File

@@ -32,7 +32,8 @@ const char * intr_types[] = {
#elif IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_KERN)
[0x40] = "IDE\t", "SATA\t",
[0x50] = "GPPInt0\t", "GPPInt1\t", "GPPInt2\t", "GPPInt3\t",
[0x75] = NULL
[0x62] = "GPIO\t",
[0x70] = "I2C0\t", "I2C1\t", "I2C2\t","I2C3\t", "UART0\t", "UART1\t",
#endif
};