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cpu/amd: Add CC6 support

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This patch adds CC6 power save support to the AMD Family 15h
support code.  As CC6 is a complex power saving state that
relies heavily on CPU, northbridge, and southbridge cooperation,
this patch alters significant amounts of code throughout the
tree simultaneously.

Allowing the CPU to enter CC6 allows the second level of turbo
boost to be reached, and also provides significant power savings
when the system is idle due to the complete core shutdown.

Change-Id: I44ce157cda97fb85f3e8f3d7262d4712b5410670
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11979
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This commit is contained in:
Timothy Pearson
2015-06-08 19:35:06 -05:00
committed by Ronald G. Minnich
parent dd4390b6e0
commit 83abd81c8a
20 changed files with 539 additions and 196 deletions
Download Patch File Download Diff File Expand all files Collapse all files

19
src/southbridge/amd/sb700/early_setup.c
View File

@@ -268,10 +268,6 @@ void enable_fid_change_on_sb(u32 sbbusn, u32 sbdn)
byte &= ~(1<<6);
pmio_write(0x8d, byte);
byte = pmio_read(0x61);
byte &= ~0x04;
pmio_write(0x61, byte);
byte = pmio_read(0x42);
byte &= ~0x04;
pmio_write(0x42, byte);
@@ -583,6 +579,13 @@ static void sb700_devices_por_init(void)
static void sb700_pmio_por_init(void)
{
u8 byte;
uint8_t enable_c_states;
enable_c_states = 0;
#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
if (get_option(&byte, "cpu_c_states") == CB_SUCCESS)
enable_c_states = !!byte;
#endif
printk(BIOS_INFO, "sb700_pmio_por_init()\n");
/* K8KbRstEn, KB_RST# control for K8 system. */
@@ -644,6 +647,14 @@ static void sb700_pmio_por_init(void)
byte |= 1 << 0;
pmio_write(0xB2, byte);
/* Set up IOAPIC and BM_STS monitoring */
byte = pmio_read(0x61);
if (enable_c_states)
byte |= 0x4;
else
byte &= ~0x04;
pmio_write(0x61, byte);
/* NOTE: Enabling automatic C1e state switch caused failures when initializing processors */
/* Enable precision HPET clock and automatic C state switch */

5
src/southbridge/amd/sb700/fadt.c
View File

@@ -2,6 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2010 Advanced Micro Devices, Inc.
* Copyright (C) 2015 Raptor Engineering
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -22,6 +23,7 @@
#include <arch/acpi.h>
#include <arch/io.h>
#include <device/device.h>
#include <cpu/amd/powernow.h>
#include "sb700.h"
void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
@@ -152,5 +154,8 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
fadt->x_gpe1_blk.addrl = 0;
fadt->x_gpe1_blk.addrh = 0x0;
if (IS_ENABLED(CONFIG_CPU_AMD_MODEL_10XXX))
amd_powernow_update_fadt(fadt);
header->checksum = acpi_checksum((void *)fadt, sizeof(acpi_fadt_t));
}

7
src/southbridge/amd/sb700/sb700.h
View File

@@ -32,10 +32,11 @@
#define ACPI_PM_EVT_BLK (SB700_ACPI_IO_BASE + 0x00) /* 4 bytes */
#define ACPI_PM1_CNT_BLK (SB700_ACPI_IO_BASE + 0x04) /* 2 bytes */
#define ACPI_PMA_CNT_BLK (SB700_ACPI_IO_BASE + 0x0E) /* 1 byte */
#define ACPI_PM_TMR_BLK (SB700_ACPI_IO_BASE + 0x18) /* 4 bytes */
#define ACPI_GPE0_BLK (SB700_ACPI_IO_BASE + 0x10) /* 8 bytes */
#define ACPI_PMA_CNT_BLK (SB700_ACPI_IO_BASE + 0x16) /* 1 byte */
#define ACPI_PM_TMR_BLK (SB700_ACPI_IO_BASE + 0x20) /* 4 bytes */
#define ACPI_GPE0_BLK (SB700_ACPI_IO_BASE + 0x18) /* 8 bytes */
#define ACPI_CPU_CONTROL (SB700_ACPI_IO_BASE + 0x08) /* 6 bytes */
#define ACPI_CPU_P_LVL2 (ACPI_CPU_CONTROL + 0x4) /* 1 byte */
extern void pm_iowrite(u8 reg, u8 value);
extern u8 pm_ioread(u8 reg);

5
src/southbridge/amd/sb700/sm.c
View File

@@ -123,7 +123,10 @@ static void sm_init(device_t dev)
pci_write_config8(dev, 0x41, byte);
byte = pm_ioread(0x61);
byte |= 1 << 1; /* Set to enable NB/SB handshake during IOAPIC interrupt for AMD K8/K7 */
if (IS_ENABLED(CONFIG_CPU_AMD_MODEL_10XXX))
byte &= ~(1 << 1); /* Clear for non-K8 CPUs */
else
byte |= 1 << 1; /* Set to enable NB/SB handshake during IOAPIC interrupt for AMD K8/K7 */
pm_iowrite(0x61, byte);
/* disable SMI */

5
src/southbridge/amd/sb800/fadt.c
View File

@@ -2,6 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2010 Advanced Micro Devices, Inc.
* Copyright (C) 2015 Raptor Engineering
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -22,6 +23,7 @@
#include <arch/acpi.h>
#include <arch/io.h>
#include <device/device.h>
#include <cpu/amd/powernow.h>
#include "sb800.h"
void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
@@ -152,5 +154,8 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
fadt->x_gpe1_blk.addrl = 0;
fadt->x_gpe1_blk.addrh = 0x0;
if (IS_ENABLED(CONFIG_CPU_AMD_MODEL_10XXX))
amd_powernow_update_fadt(fadt);
header->checksum = acpi_checksum((void *)fadt, sizeof(acpi_fadt_t));
}

8
src/southbridge/amd/sb800/sb800.h
View File

@@ -2,6 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2010 Advanced Micro Devices, Inc.
* Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -31,10 +32,11 @@
#define ACPI_PM_EVT_BLK (SB800_ACPI_IO_BASE + 0x00) /* 4 bytes */
#define ACPI_PM1_CNT_BLK (SB800_ACPI_IO_BASE + 0x04) /* 2 bytes */
#define ACPI_PMA_CNT_BLK (SB800_ACPI_IO_BASE + 0x0F) /* 1 byte */
#define ACPI_PM_TMR_BLK (SB800_ACPI_IO_BASE + 0x18) /* 4 bytes */
#define ACPI_GPE0_BLK (SB800_ACPI_IO_BASE + 0x10) /* 8 bytes */
#define ACPI_PMA_CNT_BLK (SB800_ACPI_IO_BASE + 0x17) /* 1 byte */
#define ACPI_PM_TMR_BLK (SB800_ACPI_IO_BASE + 0x20) /* 4 bytes */
#define ACPI_GPE0_BLK (SB800_ACPI_IO_BASE + 0x18) /* 8 bytes */
#define ACPI_CPU_CONTROL (SB800_ACPI_IO_BASE + 0x08) /* 6 bytes */
#define ACPI_CPU_P_LVL2 (ACPI_CPU_CONTROL + 0x4) /* 1 byte */
void pm_iowrite(u8 reg, u8 value);
u8 pm_ioread(u8 reg);