sravan/system76-coreboot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

cpu/amd: Add CC6 support

Browse Source 
This patch adds CC6 power save support to the AMD Family 15h
support code.  As CC6 is a complex power saving state that
relies heavily on CPU, northbridge, and southbridge cooperation,
this patch alters significant amounts of code throughout the
tree simultaneously.

Allowing the CPU to enter CC6 allows the second level of turbo
boost to be reached, and also provides significant power savings
when the system is idle due to the complete core shutdown.

Change-Id: I44ce157cda97fb85f3e8f3d7262d4712b5410670
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11979
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This commit is contained in:
Timothy Pearson
2015-06-08 19:35:06 -05:00
committed by Ronald G. Minnich
parent dd4390b6e0
commit 83abd81c8a
20 changed files with 539 additions and 196 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
src/southbridge/amd/sb700/sm.c
View File

@@ -123,7 +123,10 @@ static void sm_init(device_t dev)
pci_write_config8(dev, 0x41, byte);
byte = pm_ioread(0x61);
byte |= 1 << 1; /* Set to enable NB/SB handshake during IOAPIC interrupt for AMD K8/K7 */
if (IS_ENABLED(CONFIG_CPU_AMD_MODEL_10XXX))
byte &= ~(1 << 1); /* Clear for non-K8 CPUs */
else
byte |= 1 << 1; /* Set to enable NB/SB handshake during IOAPIC interrupt for AMD K8/K7 */
pm_iowrite(0x61, byte);
/* disable SMI */