sravan/system76-coreboot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

acpi: Upgrade acpi generate header

Browse Source 
Sync acpigen.h content to match with laetst acpica, the link is
https://github.com/acpica/acpica/blob/master/source/include/amlcode.h,
and revision is 20190405. The purspose of the change is just make spec
up to date.

Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: If5f5da70eb66472ddf5df0d72ca85de41faac128
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32328
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Lijian Zhao
2019-04-15 17:37:28 -07:00
committed by Duncan Laurie
parent f3ea181d98
commit 83ad5a998d
1 changed files with 84 additions and 13 deletions
Download Patch File Download Diff File Expand all files Collapse all files

97
src/arch/x86/include/arch/acpigen.h
View File

@@ -42,29 +42,57 @@
/* ACPI Op/Prefix Codes */
enum {
ZERO_OP = 0x00,
ZERO_OP = 0x00,
ONE_OP = 0x01,
NAME_OP = 0x08,
SCOPE_OP = 0x10,
BUFFER_OP = 0x11,
ALIAS_OP = 0x06,
NAME_OP = 0x08,
BYTE_PREFIX = 0x0A,
WORD_PREFIX = 0x0B,
DWORD_PREFIX = 0x0C,
STRING_PREFIX = 0x0D,
QWORD_PREFIX = 0x0E,
SCOPE_OP = 0x10,
BUFFER_OP = 0x11,
PACKAGE_OP = 0x12,
VARIABLE_PACKAGE_OP = 0x13,
METHOD_OP = 0x14,
EXTERNAL_OP = 0x15,
DUAL_NAME_PREFIX = 0x2E,
MULTI_NAME_PREFIX = 0x2F,
EXT_OP_PREFIX = 0x5B,
MUTEX_OP = 0x01,
EVENT_OP = 0x01,
SF_RIGHT_OP = 0x10,
SF_LEFT_OP = 0x11,
COND_REFOF_OP = 0x12,
CREATEFIELD_OP = 0x13,
LOAD_TABLE_OP = 0x1f,
LOAD_OP = 0x20,
STALL_OP = 0x21,
SLEEP_OP = 0x22,
ACQUIRE_OP = 0x23,
SIGNAL_OP = 0x24,
WAIT_OP = 0x25,
RST_OP = 0x26,
RELEASE_OP = 0x27,
FROM_BCD_OP = 0x28,
TO_BCD_OP = 0x29,
UNLOAD_OP = 0x2A,
REVISON_OP = 0x30,
DEBUG_OP = 0x31,
FATAL_OP = 0x32,
TIMER_OP = 0x33,
OPREGION_OP = 0x80,
FIELD_OP = 0x81,
DEVICE_OP = 0x82,
PROCESSOR_OP = 0x83,
POWER_RES_OP = 0x84,
THERMAL_ZONE_OP = 0x85,
INDEX_FIELD_OP = 0x86,
BANK_FIELD_OP = 0x87,
DATA_REGION_OP = 0x88,
ROOT_PREFIX = 0x5C,
PARENT_PREFIX = 0x5D,
LOCAL0_OP = 0x60,
LOCAL1_OP = 0x61,
LOCAL2_OP = 0x62,
@@ -73,29 +101,68 @@ enum {
LOCAL5_OP = 0x65,
LOCAL6_OP = 0x66,
LOCAL7_OP = 0x67,
ARG0_OP = 0x68,
ARG1_OP = 0x69,
ARG2_OP = 0x6A,
ARG3_OP = 0x6B,
ARG4_OP = 0x6C,
ARG5_OP = 0x6D,
ARG6_OP = 0x6E,
ARG0_OP = 0x68,
ARG1_OP = 0x69,
ARG2_OP = 0x6A,
ARG3_OP = 0x6B,
ARG4_OP = 0x6C,
ARG5_OP = 0x6D,
ARG6_OP = 0x6E,
STORE_OP = 0x70,
REF_OF_OP = 0x71,
ADD_OP = 0x72,
CONCATENATE_OP = 0x73,
SUBTRACT_OP = 0x74,
INCREMENT_OP = 0x75,
DECREMENT_OP = 0x76,
MULTIPLY_OP = 0x77,
DIVIDE_OP = 0x78,
SHIFT_LEFT_OP = 0x79,
SHIFT_RIGHT_OP = 0x7A,
AND_OP = 0x7B,
NAND_OP = 0x7C,
OR_OP = 0x7D,
NOR_OP = 0x7E,
XOR_OP = 0x7F,
NOT_OP = 0x80,
FD_SHIFT_LEFT_BIT_OR = 0x81,
FD_SHIFT_RIGHT_BIT_OR = 0x82,
DEREF_OP = 0x83,
CONCATENATE_TEMP_OP = 0x84,
MOD_OP = 0x85,
NOTIFY_OP = 0x86,
SIZEOF_OP = 0x87,
INDEX_OP = 0x88,
MATCH_OP = 0x89,
CREATE_DWORD_OP = 0x8A,
CREATE_WORD_OP = 0x8B,
CREATE_BYTE_OP = 0x8C,
CREATE_BIT_OP = 0x8D,
OBJ_TYPE_OP = 0x8E,
CREATE_QWORD_OP = 0x8F,
LAND_OP = 0x90,
LOR_OP = 0x91,
LNOT_OP = 0x92,
LEQUAL_OP = 0x93,
LGREATER_OP = 0x94,
LLESS_OP = 0x95,
TO_BUFFER_OP = 0x96,
TO_DEC_STRING_OP = 0x97,
TO_HEX_STRING_OP = 0x98,
TO_INTEGER_OP = 0x99,
TO_STRING_OP = 0x9C,
CP_OBJ_OP = 0x9D,
MID_OP = 0x9E,
CONTINUE_OP = 0x9F,
IF_OP = 0xA0,
ELSE_OP = 0xA1,
ELSE_OP = 0xA1,
WHILE_OP = 0xA2,
NOOP_OP = 0xA3,
RETURN_OP = 0xA4,
ONES_OP = 0xFF,
BREAK_OP = 0xA5,
COMMENT_OP = 0xA9,
BREAKPIONT_OP = 0xCC,
ONES_OP = 0xFF,
};
#define FIELDLIST_OFFSET(X) { .type = OFFSET, \
@@ -146,6 +213,10 @@ enum region_space {
CMOS,
PCIBARTARGET,
IPMI,
GPIO_REGION,
GPSERIALBUS,
PCC,
FIXED_HARDWARE = 0x7F,
REGION_SPACE_MAX,
};