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- O2, enums, and switch statements work in romcc

Browse Source 
- Support for compiling romcc on non x86 platforms
  - new romc options -msse and -mmmx for specifying extra registers to use
  - Bug fixes to device the device disable/enable framework and an amd8111 implementation
  - Move the link specification to the chip specification instead of the path
  - Allow specifying devices with internal bridges.
  - Initial via epia support
 - Opteron errata fixes


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1200 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Eric Biederman
2003-10-11 06:20:25 +00:00
parent 080038bfbd
commit 83b991afff
90 changed files with 8036 additions and 1974 deletions
Download Patch File Download Diff File Expand all files Collapse all files

9
NEWS
View File

@ -1,3 +1,12 @@
- 1.1.5
- O2, enums, and switch statements work in romcc
- Support for compiling romcc on non x86 platforms
- new romc options -msse and -mmmx for specifying extra registers to use
- Bug fixes to device the device disable/enable framework and an amd8111 implementation
- Move the link specification to the chip specification instead of the path
- Allow specifying devices with internal bridges.
- Initial via epia support
- Opteron errata fixes
- 1.1.4
Major restructuring of hypertransport handling.
Major rewerite of superio/NSC/pc87360 as a proof of concept for handling superio resources dynamically

2
src/arch/i386/lib/console.inc
View File

@ -526,5 +526,7 @@ console_tx_string:
jmp console_tx_string
console0:
#if 0
CONSOLE_INFO_TX_STRING($console_test)
#endif

1
src/boot/hardwaremain.c
View File

@ -160,7 +160,6 @@ void hardwaremain(int boot_complete)
/* If we have already booted attempt a hard reboot */
if (boot_complete) {
printk_spew("calling hard_reset\n");
hard_reset();
}
CONFIGURE(CONF_PASS_PRE_PCI);

4
src/config/Config.lb
View File

@ -7,7 +7,7 @@ makedefine LIBGCC_FILE_NAME := $(shell $(CC) -print-libgcc-file-name)
makedefine GCC_INC_DIR := $(shell $(CC) -print-search-dirs | sed -ne "s/install: \(.*\)/\1include/gp")
makedefine CPPFLAGS := -I$(TOP)/src/include -I$(TOP)/src/arch/$(ARCH)/include -I$(GCC_INC_DIR) $(CPUFLAGS)
makedefine ROMCCPPFLAGS := -D__ROMCC__=0 -D__ROMCC_MINOR__=34
makedefine ROMCCPPFLAGS := -D__ROMCC__=0 -D__ROMCC_MINOR__=36
makedefine CFLAGS := $(CPU_OPT) $(CPPFLAGS) -Os -nostdinc -nostdlib -fno-builtin -Wall
makedefine HOSTCFLAGS:= -Os -Wall
@ -116,7 +116,7 @@ end
makerule ./romcc
depends "$(TOP)/util/romcc/romcc.c"
action "$(HOSTCC) -g $(HOSTCFLAGS) -DVERSION='\"0.34\"' -DRELEASE_DATE='\"4 July 2003\"' $< -o $@"
action "$(HOSTCC) -g $(HOSTCFLAGS) -DVERSION='\"0.36\"' -DRELEASE_DATE='\"10 October 2003\"' $< -o $@"
end
makerule build_opt_tbl

2
src/config/Options.lb
View File

@ -117,7 +117,7 @@ define OBJCOPY
comment "Objcopy command"
end
define LINUXBIOS_VERSION
default "1.1.4"
default "1.1.5"
export always
comment "LinuxBIOS version"
end

147
src/cpu/k8/cpufixup.c
View File

@ -4,15 +4,67 @@
#include <cpu/p6/msr.h>
#include <cpu/k8/mtrr.h>
#include <device/device.h>
#include "../../northbridge/amd/amdk8/cpu_rev.c"
#include <device/chip.h>
#include "chip.h"
#define MCI_STATUS 0x401
static inline void disable_cache(void)
{
unsigned int tmp;
/* Disable cache */
/* Write back the cache and flush TLB */
asm volatile (
"movl %%cr0, %0\n\t"
"orl $0x40000000, %0\n\t"
"wbinvd\n\t"
"movl %0, %%cr0\n\t"
"wbinvd\n\t"
:"=r" (tmp)
::"memory");
}
static inline void enable_cache(void)
{
unsigned int tmp;
// turn cache back on.
asm volatile (
"movl %%cr0, %0\n\t"
"andl $0x9fffffff, %0\n\t"
"movl %0, %%cr0\n\t"
:"=r" (tmp)
::"memory");
}
static inline msr_t rdmsr_amd(unsigned index)
{
msr_t result;
__asm__ __volatile__ (
"rdmsr"
: "=a" (result.lo), "=d" (result.hi)
: "c" (index), "D" (0x9c5a203a)
);
return result;
}
static inline void wrmsr_amd(unsigned index, msr_t msr)
{
__asm__ __volatile__ (
"wrmsr"
: /* No outputs */
: "c" (index), "a" (msr.lo), "d" (msr.hi), "D" (0x9c5a203a)
);
}
void k8_cpufixup(struct mem_range *mem)
{
unsigned long mmio_basek, tomk;
unsigned long i;
msr_t msr;
disable_cache();
/* Except for the PCI MMIO hold just before 4GB there are no
* significant holes in the address space, so just account
* for those two and move on.
@ -32,28 +84,15 @@ void k8_cpufixup(struct mem_range *mem)
mmio_basek = tomk;
}
#if 1
/* Report the amount of memory. */
print_debug("cpufixup RAM: 0x");
print_debug_hex32(tomk);
print_debug(" KB\r\n");
#endif
/* Now set top of memory */
msr.lo = (tomk & 0x003fffff) << 10;
msr.hi = (tomk & 0xffc00000) >> 22;
wrmsr(TOP_MEM2, msr);
/* Leave a 64M hole between TOP_MEM and TOP_MEM2
* so I can see my rom chip and other I/O devices.
*/
if (tomk >= 0x003f0000) {
tomk = 0x3f0000;
} // tom_k = 0x3c0000;
msr.lo = (tomk & 0x003fffff) << 10;
msr.hi = (tomk & 0xffc00000) >> 22;
/* Setup TOP_MEM */
msr.hi = mmio_basek >> 22;
msr.lo = mmio_basek << 10;
wrmsr(TOP_MEM, msr);
/* Setup TOP_MEM2 */
msr.hi = tomk >> 22;
msr.lo = tomk << 10;
wrmsr(TOP_MEM2, msr);
/* zero the IORR's before we enable to prevent
* undefined side effects.
@ -66,6 +105,64 @@ void k8_cpufixup(struct mem_range *mem)
msr = rdmsr(SYSCFG_MSR);
msr.lo |= SYSCFG_MSR_MtrrVarDramEn | SYSCFG_MSR_TOM2En;
wrmsr(SYSCFG_MSR, msr);
/* zero the machine check error status registers */
msr.lo = 0;
msr.hi = 0;
for(i=0; i<5; i++) {
wrmsr(MCI_STATUS + (i*4),msr);
}
if (is_cpu_pre_c0()) {
/* Erratum 63... */
msr = rdmsr(HWCR_MSR);
msr.lo |= (1 << 6);
wrmsr(HWCR_MSR, msr);
/* Erratum 69... */
#if 1
msr = rdmsr_amd(BU_CFG_MSR);
msr.hi |= (1 << (45 - 32));
wrmsr_amd(BU_CFG_MSR, msr);
#endif
/* Erratum 81... */
#if 1
msr = rdmsr_amd(DC_CFG_MSR);
msr.lo |= (1 << 10);
wrmsr_amd(DC_CFG_MSR, msr);
#endif
}
/* Erratum 89 ... */
msr = rdmsr(NB_CFG_MSR);
msr.lo |= 1 << 3;
if (!is_cpu_pre_c0()) {
/* Erratum 86 Disable data masking on C0 and
* later processor revs.
* FIXME this is only needed if ECC is enabled.
*/
msr.hi |= 1 << (36 - 32);
}
wrmsr(NB_CFG_MSR, msr);
#if 1 /* The following erratum fixes reset the cpu ???? */
/* Erratum 97 ... */
if (!is_cpu_pre_c0()) {
msr = rdmsr_amd(DC_CFG_MSR);
msr.lo |= 1 << 3;
wrmsr_amd(DC_CFG_MSR, msr);
}
/* Erratum 94 ... */
msr = rdmsr_amd(IC_CFG_MSR);
msr.lo |= 1 << 11;
wrmsr_amd(IC_CFG_MSR, msr);
#endif
/* Erratum 91 prefetch miss is handled in the kernel */
enable_cache();
}
static
@ -87,10 +184,6 @@ void k8_enable(struct chip *chip, enum chip_pass pass)
}
struct chip_control cpu_k8_control = {
enable: k8_enable,
name: "AMD K8"
.enable = k8_enable,
.name = "AMD K8",
};

2
src/cpu/p6/mtrr.c
View File

@ -92,7 +92,7 @@ static void intel_set_var_mtrr(unsigned int reg, unsigned long basek, unsigned l
base.lo = basek << 10;
if (sizek < 4*1024*1024) {
mask.hi = 0x0F;
mask.hi = 0x0FF;
mask.lo = ~((sizek << 10) -1);
}
else {

30
src/devices/chip.c
View File

@ -46,16 +46,33 @@ void chip_enumerate(struct chip *chip)
int identical_paths;
identical_paths =
(i > 0) &&
(path_eq(&chip->path[i - 1].path, &chip->path[i].path)) &&
(chip->path[i - 1].channel == chip->path[i].channel);
(path_eq(&chip->path[i - 1].path, &chip->path[i].path));
if (!identical_paths) {
struct bus *parent;
int bus;
link = 0;
dev = 0;
parent = chip->bus;
switch(chip->path[i].path.type) {
case DEVICE_PATH_NONE:
break;
case DEVICE_PATH_PCI:
bus = chip->path[i].path.u.pci.bus;
if (bus != 0) {
device_t dev;
int i = 1;
dev = chip->dev;
while(dev && (i != bus)) {
dev = dev->next;
i++;
}
if ((i == bus) && dev) {
parent = &dev->link[0];
}
}
/* Fall through */
default:
dev = alloc_dev(chip->bus, &chip->path[i].path);
dev = alloc_dev(parent, &chip->path[i].path);
break;
}
}
@ -63,12 +80,13 @@ void chip_enumerate(struct chip *chip)
link += 1;
}
if (dev) {
printk_spew("path %s %s\n", dev_path(dev), identical_paths?"identical":"");
printk_spew("path (%p) %s %s", dev, dev_path(dev), identical_paths?"identical":"");
printk_spew(" parent: (%p) %s\n",dev->bus->dev, dev_path(dev->bus->dev));
dev->chip = chip;
dev->enable = chip->path[i].enable;
dev->links = link + 1;
for(child = chip->children; child; child = child->next) {
if (!child->bus &&
child->path[0].channel == i) {
if (!child->bus && child->link == i) {
child->bus = &dev->link[link];
}
}

22
src/devices/device.c
View File

@ -115,6 +115,9 @@ static void read_resources(struct bus *bus)
dev_path(curdev));
continue;
}
if (!curdev->enable) {
continue;
}
curdev->ops->read_resources(curdev);
/* Read in subtractive resources behind the current device */
links = 0;
@ -251,17 +254,13 @@ void compute_allocate_resource(
min_align = 0;
base = bridge->base;
printk_spew("%s: bus %p, bridge %p, type_mask 0x%x, type 0x%x\n",
__FUNCTION__,
bus, bridge, type_mask, type);
printk_spew("vendor 0x%x device 0x%x class 0x%x \n",
bus->dev->vendor, bus->dev->device, bus->dev->class);
printk_spew("%s compute_allocate_%s: base: %08lx size: %08lx align: %d gran: %d\n",
dev_path(bus->dev),
(bridge->flags & IORESOURCE_IO)? "io":
(bridge->flags & IORESOURCE_PREFETCH)? "prefmem" : "mem",
base, bridge->size, bridge->align, bridge->gran);
/* We want different minimum alignments for different kinds of
* resources. These minimums are not device type specific
* but resource type specific.
@ -406,6 +405,9 @@ void assign_resources(struct bus *bus)
dev_path(curdev));
continue;
}
if (!curdev->enable) {
continue;
}
curdev->ops->set_resources(curdev);
}
printk_debug("ASSIGNED RESOURCES, bus %d\n", bus->secondary);
@ -422,6 +424,9 @@ void enable_resources(struct device *dev)
dev_path(dev));
return;
}
if (!dev->enable) {
return;
}
dev->ops->enable_resources(dev);
}
@ -444,13 +449,12 @@ void dev_enumerate(void)
void dev_configure(void)
{
struct device *root = &dev_root;
printk_info("%s: Allocating resources...", __FUNCTION__);
printk_info("Allocating resources...");
printk_debug("\n");
root->ops->read_resources(root);
printk_spew("%s: done reading resources...\n", __FUNCTION__);
/* Make certain the io devices are allocated somewhere
* safe.
*/
@ -465,10 +469,8 @@ void dev_configure(void)
root->resource[1].flags |= IORESOURCE_SET;
// now just set things into registers ... we hope ...
root->ops->set_resources(root);
printk_spew("%s: done setting resources...\n", __FUNCTION__);
allocate_vga_resource();
printk_spew("%s: done vga resources...\n", __FUNCTION__);
printk_info("done.\n");
}
@ -494,7 +496,7 @@ void dev_initialize(void)
printk_info("Initializing devices...\n");
for (dev = all_devices; dev; dev = dev->next) {
if (dev->ops && dev->ops->init) {
if (dev->enable && dev->ops && dev->ops->init) {
printk_debug("%s init\n", dev_path(dev));
dev->ops->init(dev);
}

15
src/devices/device_util.c
View File

@ -30,15 +30,17 @@ device_t alloc_find_dev(struct bus *parent, struct device_path *path)
*/
struct device *dev_find_slot(unsigned int bus, unsigned int devfn)
{
struct device *dev;
struct device *dev, *result;
result = 0;
for (dev = all_devices; dev; dev = dev->next) {
if ((dev->bus->secondary == bus) &&
(dev->path.u.pci.devfn == devfn)) {
result = dev;
break;
}
}
return dev;
return result;
}
/** Find a device of a given vendor and type
@ -88,6 +90,9 @@ const char *dev_path(device_t dev)
}
else {
switch(dev->path.type) {
case DEVICE_PATH_ROOT:
memcpy(buffer, "Root Device", 12);
break;
case DEVICE_PATH_PCI:
sprintf(buffer, "PCI: %02x:%02x.%01x",
dev->bus->secondary,
@ -116,8 +121,12 @@ int path_eq(struct device_path *path1, struct device_path *path2)
switch(path1->type) {
case DEVICE_PATH_NONE:
break;
case DEVICE_PATH_ROOT:
equal = 1;
break;
case DEVICE_PATH_PCI:
equal = path1->u.pci.devfn == path2->u.pci.devfn;
equal = (path1->u.pci.bus == path2->u.pci.bus) &&
(path1->u.pci.devfn == path2->u.pci.devfn);
break;
case DEVICE_PATH_PNP:
equal = (path1->u.pnp.port == path2->u.pnp.port) &&

16
src/devices/hypertransport.c
View File

@ -4,6 +4,7 @@
#include <device/path.h>
#include <device/pci.h>
#include <device/hypertransport.h>
#include <device/chip.h>
#include <part/hard_reset.h>
#include <part/fallback_boot.h>
@ -243,11 +244,19 @@ unsigned int hypertransport_scan_chain(struct bus *bus, unsigned int max)
/* Add this device to the pci bus chain */
*chain_last = dev;
/* Run the magice enable/disable sequence for the device */
if (dev->ops && dev->ops->enable) {
dev->ops->enable(dev);
if (dev->chip && dev->chip->control && dev->chip->control->enable_dev) {
dev->chip->control->enable_dev(dev);
}
/* Now read the vendor and device id */
id = pci_read_config32(dev, PCI_VENDOR_ID);
/* If the chain is fully enumerated quit */
if (id == 0xffffffff || id == 0x00000000 ||
id == 0x0000ffff || id == 0xffff0000) {
printk_err("Missing static device: %s\n",
dev_path(dev));
break;
}
}
/* Update the device chain tail */
for(func = dev; func; func = func->sibling) {
@ -268,7 +277,8 @@ unsigned int hypertransport_scan_chain(struct bus *bus, unsigned int max)
/* Find the hypertransport link capability */
pos = ht_lookup_slave_capability(dev);
if (pos == 0) {
printk_err("Hypertransport link capability not found");
printk_err("%s Hypertransport link capability not found",
dev_path(dev));
break;
}

19
src/devices/pci_device.c
View File

@ -18,6 +18,7 @@
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/chip.h>
#include <part/hard_reset.h>
#include <part/fallback_boot.h>
@ -175,7 +176,6 @@ static void pci_bridge_read_bases(struct device *dev)
/* FIXME handle bridges without some of the optional resources */
printk_spew("%s: path %s\n", __FUNCTION__, dev_path(dev));
/* Initialize the io space constraints on the current bus */
dev->resource[reg].base = 0;
dev->resource[reg].size = 0;
@ -215,7 +215,6 @@ static void pci_bridge_read_bases(struct device *dev)
reg++;
dev->resources = reg;
printk_spew("DONE %s: path %s\n", __FUNCTION__, dev_path(dev));
}
@ -455,12 +454,14 @@ static void set_pci_ops(struct device *dev)
break;
default:
bad:
if (dev->enable) {
printk_err("%s [%04x/%04x/%06x] has unknown header "
"type %02x, ignoring.\n",
dev_path(dev),
dev->vendor, dev->device,
dev->class >> 8, dev->hdr_type);
}
}
return;
}
@ -556,13 +557,12 @@ unsigned int pci_scan_bus(struct bus *bus,
}
else {
/* Run the magic enable/disable sequence for the device */
if (dev->ops && dev->ops->enable) {
dev->ops->enable(dev);
if (dev->chip && dev->chip->control && dev->chip->control->enable_dev) {
dev->chip->control->enable_dev(dev);
}
/* Now read the vendor and device id */
id = pci_read_config32(dev, PCI_VENDOR_ID);
}
/* Read the rest of the pci configuration information */
hdr_type = pci_read_config8(dev, PCI_HEADER_TYPE);
class = pci_read_config32(dev, PCI_CLASS_REVISION);
@ -576,21 +576,20 @@ unsigned int pci_scan_bus(struct bus *bus,
/* Look at the vendor and device id, or at least the
* header type and class and figure out which set of configuration
* methods to use.
* methods to use. Unless we already have some pci ops.
*/
if (!dev->ops) {
set_pci_ops(dev);
/* Error if we don't have some pci operations for it */
if (!dev->ops) {
if (dev->enable && !dev->ops) {
printk_err("%s No device operations\n",
dev_path(dev));
continue;
}
/* Now run the magic enable/disable sequence for the device */
if (dev->ops && dev->ops->enable) {
dev->ops->enable(dev);
}
}
printk_debug("%s [%04x/%04x] %s\n",
dev_path(dev),
@ -633,7 +632,6 @@ unsigned int pci_scan_bridge(struct device *dev, unsigned int max)
uint32_t buses;
uint16_t cr;
printk_spew("%s: dev %p, max %d\n", __FUNCTION__, dev, max);
bus = &dev->link[0];
dev->links = 1;
@ -707,7 +705,6 @@ static void pci_level_irq(unsigned char intNum)
}
}
/*
This function assigns IRQs for all functions contained within
the indicated device address. If the device does not exist or does

2
src/devices/root_device.c
View File

@ -123,6 +123,8 @@ struct device_operations default_dev_ops_root = {
struct device dev_root = {
.ops = &default_dev_ops_root,
.bus = &dev_root.link[0],
.path = { .type = DEVICE_PATH_ROOT },
.enable = 1,
.links = 1,
.link = {
[0] = {

4
src/include/cpu/k8/mtrr.h
View File

@ -30,5 +30,9 @@
#define TOP_MEM 0xC001001A
#define TOP_MEM2 0xC001001D
#define HWCR_MSR 0xC0010015
#define NB_CFG_MSR 0xC001001f
#define IC_CFG_MSR 0xC0011021
#define DC_CFG_MSR 0xC0011022
#define BU_CFG_MSR 0xC0011023
#endif /* CPU_K8_MTRR_H */

3
src/include/device/chip.h
View File

@ -49,6 +49,7 @@ enum chip_pass {
*/
struct chip;
struct device;
/* there is one of these for each TYPE of chip */
struct chip_control {
@ -56,6 +57,7 @@ struct chip_control {
char *name;
void (*enable)(struct chip *, enum chip_pass);
void (*enumerate)(struct chip *chip);
void (*enable_dev)(struct device *dev);
};
@ -72,6 +74,7 @@ struct bus;
#define MAX_CHIP_PATHS 16
#endif
struct chip {
unsigned link;
struct chip_control *control; /* for this device */
struct chip_device_path path[MAX_CHIP_PATHS]; /* can be 0, in which case the default is taken */
char *configuration; /* can be 0. */

4
src/include/device/device.h
View File

@ -35,6 +35,7 @@ struct bus {
* combination:
*/
struct chip;
struct device {
struct bus * bus; /* bus this device is on */
device_t sibling; /* next device on this bus */
@ -72,6 +73,7 @@ struct device {
unsigned long rom_address;
struct device_operations *ops;
struct chip *chip;
};
extern struct device dev_root; /* root bus */
@ -94,7 +96,7 @@ extern void enumerate_static_device(void);
extern const char *dev_path(device_t dev);
/* Helper functions */
device_t alloc_find_dev(struct bus *bus, struct device_path *path);
device_t alloc_find_dev(struct bus *parent, struct device_path *path);
device_t dev_find_device (unsigned int vendor, unsigned int device, device_t from);
device_t dev_find_class (unsigned int class, device_t from);
device_t dev_find_slot (unsigned int bus, unsigned int devfn);

2
src/include/device/path.h
View File

@ -3,6 +3,7 @@
enum device_path_type {
DEVICE_PATH_NONE = 0,
DEVICE_PATH_ROOT,
DEVICE_PATH_PCI,
DEVICE_PATH_PNP,
DEVICE_PATH_I2C,
@ -10,6 +11,7 @@ enum device_path_type {
struct pci_path
{
unsigned bus;
unsigned devfn;
};

4
src/mainboard/amd/quartet/mptable.c
View File

@ -7,8 +7,8 @@
void *smp_write_config_table(void *v, unsigned long * processor_map)
{
static const char sig[4] = "PCMP";
static const char oem[8] = "LNXI ";
static const char productid[12] = "HDAMA ";
static const char oem[8] = "AMD ";
static const char productid[12] = "QUARTET ";
struct mp_config_table *mc;
unsigned char bus_num;
unsigned char bus_isa;

46
src/mainboard/arima/hdama/Config.lb
View File

@ -161,7 +161,7 @@ makerule ./auto.E
end
makerule ./auto.inc
depends "./auto.E ./romcc"
action "./romcc -mcpu=k8 -O ./auto.E > auto.inc"
action "./romcc -mcpu=k8 -O2 ./auto.E > auto.inc"
end
##
@ -231,32 +231,36 @@ northbridge amd/amdk8 "mc0"
pci 0:18.1
pci 0:18.2
pci 0:18.3
southbridge amd/amd8131 "amd8131"
southbridge amd/amd8131 "amd8131" link 0
pci 0:0.0
pci 0:0.1
pci 0:1.0
pci 0:1.1
end
southbridge amd/amd8111 "amd8111"
southbridge amd/amd8111 "amd8111" link 0
pci 0:0.0
pci 0:1.0
pci 0:1.1
pci 0:1.2
pci 0:1.3
pci 0:1.5
pci 0:1.6
superio NSC/pc87360
pnp 1:2e.0
pnp 1:2e.1
pnp 1:2e.2
pnp 1:2e.3
pnp 1:2e.4
pnp 1:2e.5
pnp 1:2e.6
pnp 1:2e.7
pnp 1:2e.8
pnp 1:2e.9
pnp 1:2e.a
pci 0:1.0 on
pci 0:1.1 on
pci 0:1.2 on
pci 0:1.3 on
pci 0:1.5 off
pci 0:1.6 off
pci 1:0.0 on
pci 1:0.1 on
pci 1:0.2 on
pci 1:1.0 off
superio NSC/pc87360 link 1
pnp 2e.0
pnp 2e.1
pnp 2e.2
pnp 2e.3
pnp 2e.4
pnp 2e.5
pnp 2e.6
pnp 2e.7
pnp 2e.8
pnp 2e.9
pnp 2e.a
register "com1" = "{1, 0, 0x3f8, 4}"
register "lpt" = "{1}"
end

21
src/mainboard/arima/hdama/auto.c
View File

@ -1,5 +1,4 @@
#define ASSEMBLY 1
#include <stdint.h>
#include <device/pci_def.h>
#include <cpu/p6/apic.h>
@ -17,26 +16,33 @@
#include "cpu/p6/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "debug.c"
#include "northbridge/amd/amdk8/cpu_rev.c"
#define SIO_BASE 0x2e
#define MAXIMUM_CONSOLE_LOGLEVEL 9
#define DEFAULT_CONSOLE_LOGLEVEL 9
static void memreset_setup(void)
{
if (is_cpu_pre_c0()) {
/* Set the memreset low */
outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28);
/* Ensure the BIOS has control of the memory lines */
outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29);
}
else {
/* Ensure the CPU has controll of the memory lines */
outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 29);
}
}
static void memreset(int controllers, const struct mem_controller *ctrl)
{
if (is_cpu_pre_c0()) {
udelay(800);
/* Set memreset_high */
outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28);
udelay(90);
}
}
static unsigned int generate_row(uint8_t node, uint8_t row, uint8_t maxnodes)
{
@ -92,9 +98,6 @@ static void coherent_ht_mainboard(unsigned cpus)
{
}
#include "northbridge/amd/amdk8/cpu_ldtstop.c"
#include "southbridge/amd/amd8111/amd8111_ldtstop.c"
#include "northbridge/amd/amdk8/raminit.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "sdram/generic_sdram.c"
@ -201,7 +204,7 @@ static void main(void)
enumerate_ht_chain(0);
distinguish_cpu_resets(0);
#if 1
#if 0
print_pci_devices();
#endif
enable_smbus();
@ -211,10 +214,10 @@ static void main(void)
memreset_setup();
sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
#if 1
#if 0
dump_pci_devices();
#endif
#if 1
#if 0
dump_pci_device(PCI_DEV(0, 0x18, 2));
#endif

4
src/mainboard/arima/hdama/failover.c
View File

@ -27,6 +27,10 @@ static void main(void)
asm("jmp __cpu_reset");
}
}
/* Is this a deliberate reset by the bios */
else if (bios_reset_detected() && last_boot_normal()) {
asm("jmp __normal_image");
}
/* Is this a secondary cpu? */
else if (!boot_cpu() && last_boot_normal()) {
asm("jmp __normal_image");

53
src/mainboard/arima/hdama/irq_tables.c
View File

@ -1,43 +1,34 @@
/* This file was generated by getpir.c, do not modify!
(but if you do, please run checkpir on it to verify)
Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up
Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM
*/
#include <arch/pirq_routing.h>
const struct irq_routing_table intel_irq_routing_table = {
PIRQ_SIGNATURE, /* u32 signature */
PIRQ_VERSION, /* u16 version */
32+16*18, /* there can be total 18 devices on the bus */
32+16*9, /* there can be total 9 devices on the bus */
1, /* Where the interrupt router lies (bus) */
0x23, /* Where the interrupt router lies (dev) */
0, /* IRQs devoted exclusively to PCI usage */
(4<<3)|3, /* Where the interrupt router lies (dev) */
0x0, /* IRQs devoted exclusively to PCI usage */
0x1022, /* Vendor */
0x746b, /* Device */
0, /* Crap (miniport) */
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
0x35, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
{
{0,0xc0, {{0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0},
{0,0x50, {{0x1, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0},
{0x2,0x8, {{0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}}, 0x3, 0},
{0x2,0x10, {{0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}, {0x2, 0xdef8}}, 0x4, 0},
{0x2,0x18, {{0x4, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0x0, 0},
{0x2,0x20, {{0x4, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0x0, 0},
{0x2,0x28, {{0x2, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0xa, 0},
{0,0x58, {{0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0},
{0x3,0x8, {{0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}}, 0x1, 0},
{0x3,0x10, {{0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}, {0x2, 0xdef8}}, 0x2, 0},
{0x3,0x18, {{0x4, 0xdef8}, {0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}}, 0x9, 0},
{0,0x30, {{0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0},
{0x1,0, {{0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0x4, 0xdef8}}, 0, 0},
{0x1,0x28, {{0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}}, 0x5, 0},
{0x1,0x20, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0x6, 0},
{0x1,0x30, {{0x3, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0xb, 0},
{0,0x38, {{0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0},
{0,0xc8, {{0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0},
0xb0, /* u8 checksum , mod 256 checksum must give zero */
{ /* bus, devfn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
/* PCI Slot 1 */
{0x03, (0x01<<3)|0, {{0x02, 0xdef8}, {0x03, 0xdef8}, {0x04, 0xdef8}, {0x01, 0xdef8}}, 0x01, 0},
/* PCI Slot 2 */
{0x03, (0x02<<3)|0, {{0x03, 0xdef8}, {0x04, 0xdef8}, {0x01, 0xdef8}, {0x02, 0xdef8}}, 0x02, 0},
/* PCI Slot 3 */
{0x02, (0x01<<3)|0, {{0x02, 0xdef8}, {0x03, 0xdef8}, {0x04, 0xdef8}, {0x01, 0xdef8}}, 0x03, 0},
/* PCI Slot 4 */
{0x02, (0x02<<3)|0, {{0x03, 0xdef8}, {0x04, 0xdef8}, {0x01, 0xdef8}, {0x02, 0xdef8}}, 0x04, 0},
/* PCI Slot 5 */
{0x04, (0x05<<3)|0, {{0x02, 0xdef8}, {0x03, 0xdef8}, {0x04, 0xdef8}, {0x01, 0xdef8}}, 0x05, 0},
/* PCI Slot 6 */
{0x04, (0x04<<3)|0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x04, 0xdef8}}, 0x06, 0},
/* Onboard NICS */
{0x02, (0x03<<3)|0, {{0x04, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}}, 0x00, 0},
{0x02, (0x04<<3)|0, {{0x04, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}}, 0x00, 0},
/* Let Linux know about bus 1 */
{0x01, (0x04<<3)|3, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}}, 0x00, 0},
}
};

1
src/mainboard/arima/hdama/mainboard.c
View File

@ -1,4 +1,3 @@
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>

12
src/mainboard/arima/hdama/mptable.c
View File

@ -48,8 +48,8 @@ void *smp_write_config_table(void *v, unsigned long * processor_map)
else {
printk_debug("ERROR - could not find PCI 1:03.0, using defaults\n");
bus_8111_1 = 3;
bus_isa = 4;
bus_8111_1 = 4;
bus_isa = 5;
}
/* 8131-1 */
dev = dev_find_slot(1, PCI_DEVFN(0x01,0));
@ -60,7 +60,7 @@ void *smp_write_config_table(void *v, unsigned long * processor_map)
else {
printk_debug("ERROR - could not find PCI 1:01.0, using defaults\n");
bus_8131_1 = 1;
bus_8131_1 = 2;
}
/* 8131-2 */
dev = dev_find_slot(1, PCI_DEVFN(0x02,0));
@ -71,7 +71,7 @@ void *smp_write_config_table(void *v, unsigned long * processor_map)
else {
printk_debug("ERROR - could not find PCI 1:02.0, using defaults\n");
bus_8131_2 = 2;
bus_8131_2 = 3;
}
}
@ -144,10 +144,6 @@ void *smp_write_config_table(void *v, unsigned long * processor_map)
bus_isa, 0x00, MP_APIC_ALL, 0x01);
/* AGP Slot */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
0x03, (6<<2)|0, 0x02, 0x12);
/* PCI Slot 1 */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
bus_8131_2, (1<<2)|0, 0x02, 0x11);

1
src/northbridge/amd/amdk8/Config.lb
View File

@ -1,3 +1,4 @@
config chip.h
object northbridge.o
driver misc_control.o
driver mcf0_control.o

120
src/northbridge/amd/amdk8/coherent_ht.c
View File

@ -100,43 +100,6 @@ static void disable_probes(void)
print_debug("done.\r\n");
}
//BY LYH
#define WAIT_TIMES 1000
static void wait_ap_stop(u8 node)
{
unsigned long reg;
unsigned long i;
for(i=0;i<WAIT_TIMES;i++) {
unsigned long regx;
regx = pci_read_config32(NODE_HT(node),0x6c);
if((regx & (1<<4))==1) break;
}
reg = pci_read_config32(NODE_HT(node),0x6c);
reg &= ~(1<<4); // clear it
pci_write_config32(NODE_HT(node), 0x6c, reg);
}
static void notify_bsp_ap_is_stopped(void)
{
unsigned long reg;
unsigned long apic_id;
apic_id = *((volatile unsigned long *)(APIC_DEFAULT_BASE+APIC_ID));
apic_id >>= 24;
#if 0
print_debug("applicaton cpu apic_id: ");
print_debug_hex32(apic_id);
print_debug("\r\n");
#endif
/* AP apic_id == node_id ? */
if(apic_id != 0) {
/* set the ColdResetbit to notify BSP that AP is stopped */
reg = pci_read_config32(NODE_HT(apic_id), 0x6C);
reg |= 1<<4;
pci_write_config32(NODE_HT(apic_id), 0x6C, reg);
}
}
//BY LYH END
static void enable_routing(u8 node)
{
@ -171,13 +134,6 @@ static void enable_routing(u8 node)
val=pci_read_config32(NODE_HT(node), 0x6c);
val &= ~((1<<6)|(1<<5)|(1<<4)|(1<<1)|(1<<0));
pci_write_config32(NODE_HT(node), 0x6c, val);
//BY LYH
#if 1
if(node!=0) {
wait_ap_stop(node);
}
#endif
//BY LYH END
print_debug(" done.\r\n");
}
@ -225,6 +181,62 @@ static bool check_connection(u8 src, u8 dest, u8 link)
return 1;
}
static void optimize_connection(u8 node1, u8 link1, u8 node2, u8 link2)
{
static const uint8_t link_width_to_pow2[]= { 3, 4, 0, 5, 1, 2, 0, 0 };
static const uint8_t pow2_to_link_width[] = { 0x7, 4, 5, 0, 1, 3 };
uint16_t freq_cap1, freq_cap2, freq_cap, freq_mask;
uint8_t width_cap1, width_cap2, width_cap, width, ln_width1, ln_width2;
uint8_t freq;
/* Set link width and frequency */
/* Get the frequency capabilities */
freq_cap1 = pci_read_config16(NODE_HT(node1), 0x80 + link1 + PCI_HT_CAP_HOST_FREQ_CAP);
freq_cap2 = pci_read_config16(NODE_HT(node2), 0x80 + link2 + PCI_HT_CAP_HOST_FREQ_CAP);
/* Calculate the highest possible frequency */
#if 1
/* FIXME!!!!!!!
* This method of computing the fastes frequency is broken.
* Because the frequencies (i.e. 100Mhz) are not ordered.
*/
freq = log2(freq_cap1 & freq_cap2 & 0xff);
#else
/* Only allow supported frequencies 800Mhz and below */
freq = log2(freq_cap1 & freq_cap2 & 0x3f);
#endif
/* Set the Calulcated link frequency */
pci_write_config8(NODE_HT(node1), 0x80 + link1 + PCI_HT_CAP_HOST_FREQ, freq);
pci_write_config8(NODE_HT(node2), 0x80 + link2 + PCI_HT_CAP_HOST_FREQ, freq);
/* Get the width capabilities */
width_cap1 = pci_read_config8(NODE_HT(node1), 0x80 + link1 + PCI_HT_CAP_HOST_WIDTH);
width_cap2 = pci_read_config8(NODE_HT(node2), 0x80 + link2 + PCI_HT_CAP_HOST_WIDTH);
/* Calculate node1's input width */
ln_width1 = link_width_to_pow2[width_cap1 & 7];
ln_width2 = link_width_to_pow2[(width_cap2 >> 4) & 7];
if (ln_width1 > ln_width2) {
ln_width1 = ln_width2;
}
width = pow2_to_link_width[ln_width1];
/* Calculate node1's output width */
ln_width1 = link_width_to_pow2[(width_cap1 >> 4) & 7];
ln_width2 = link_width_to_pow2[width_cap2 & 7];
if (ln_width1 > ln_width2) {
ln_width1 = ln_width2;
}
width |= pow2_to_link_width[ln_width1] << 4;
/* Set node1's widths */
pci_write_config8(NODE_HT(node1), 0x80 + link1 + PCI_HT_CAP_HOST_WIDTH + 1, width);
/* Set node2's widths */
width = ((width & 0x70) >> 4) | ((width & 0x7) << 4);
pci_write_config8(NODE_HT(node2), 0x80 + link2 + PCI_HT_CAP_HOST_WIDTH + 1, width);
}
static void fill_row(u8 node, u8 row, u32 value)
{
#if 0
@ -346,6 +358,7 @@ static u8 setup_smp(void)
}
/* We found 2 nodes so far */
optimize_connection(0, ACROSS, 7, ACROSS);
setup_node(0, cpus); /* Node 1 is there. Setup Node 0 correctly */
setup_remote_node(1, cpus); /* Setup the routes on the remote node */
rename_temp_node(1); /* Rename Node 7 to Node 1 */
@ -444,17 +457,6 @@ static unsigned detect_mp_capabilities(unsigned cpus)
#endif
/* this is a shrunken cpuid. */
static unsigned int cpuid(unsigned int op)
{
unsigned int ret;
asm volatile ( "cpuid" : "=a" (ret) : "a" (op));
return ret;
}
static void coherent_ht_finalize(unsigned cpus)
{
int node;
@ -469,7 +471,7 @@ static void coherent_ht_finalize(unsigned cpus)
#if 1
print_debug("coherent_ht_finalize\r\n");
#endif
rev_a0=((cpuid(1)&0xffff)==0x0f10);
rev_a0= is_cpu_rev_a0();
for (node=0; node<cpus; node++) {
u32 val;
@ -479,7 +481,11 @@ static void coherent_ht_finalize(unsigned cpus)
pci_write_config32(NODE_HT(node),0x60,val);
val=pci_read_config32(NODE_HT(node), 0x68);
#if 1
val |= 0x00008000;
#else
val |= 0x0f00c800; // 0x00008000->0f00c800 BY LYH
#endif
pci_write_config32(NODE_HT(node),0x68,val);
if (rev_a0) {
@ -508,7 +514,7 @@ static int setup_coherent_ht_domain(void)
#endif
coherent_ht_finalize(cpus);
/* this should probably go away again. */
/* FIXME this should probably go away again. */
coherent_ht_mainboard(cpus);
return reset_needed;
}

25
src/northbridge/amd/amdk8/cpu_rev.c Normal file
View File

@ -0,0 +1,25 @@
/* this is a shrunken cpuid. */
static unsigned int cpuid(unsigned int op)
{
unsigned int ret;
unsigned dummy2,dummy3,dummy4;
asm volatile (
"cpuid"
: "=a" (ret), "=b" (dummy2), "=c" (dummy3), "=d" (dummy4)
: "a" (op)
);
return ret;
}
static int is_cpu_rev_a0(void)
{
return (cpuid(1) & 0xffff) == 0x0f10;
}
static int is_cpu_pre_c0(void)
{
return (cpuid(1) & 0xffef) < 0x0f48;
}

42
src/northbridge/amd/amdk8/misc_control.c
View File

@ -8,6 +8,7 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
#include "./cpu_rev.c"
static void misc_control_init(struct device *dev)
{
@ -17,7 +18,48 @@ static void misc_control_init(struct device *dev)
cmd = pci_read_config32(dev, 0x44);
cmd |= (1<<6) | (1<<25);
pci_write_config32(dev, 0x44, cmd );
if (is_cpu_pre_c0()) {
/* errata 58 */
cmd = pci_read_config32(dev, 0x80);
cmd &= ~(1<<0);
pci_write_config32(dev, 0x80, cmd );
cmd = pci_read_config32(dev, 0x84);
cmd &= ~(1<<24);
cmd &= ~(1<<8);
pci_write_config32(dev, 0x84, cmd );
/* errata 66 */
cmd = pci_read_config32(dev, 0x70);
cmd &= ~(1<<0);
cmd |= (1<<1);
pci_write_config32(dev, 0x70, cmd );
cmd = pci_read_config32(dev, 0x7c);
cmd &= ~(3<<4);
pci_write_config32(dev, 0x7c, cmd );
}
else {
/* errata 98 */
#if 0
cmd = pci_read_config32(dev, 0xd4);
if(cmd != 0x04e20707) {
cmd = 0x04e20707;
pci_write_config32(dev, 0xd4, cmd );
hard_reset();
}
#endif
cmd = 0x04e20707;
pci_write_config32(dev, 0xd4, cmd );
}
#if 1
cmd = pci_read_config32(dev, 0xdc);
if((cmd & 0x0000ff00) != 0x02500) {
cmd &= 0xffff00ff;
cmd |= 0x00002500;
pci_write_config32(dev, 0xdc, cmd );
printk_debug("resetting cpu\n");
hard_reset();
}
#endif
printk_debug("done.\n");
}

2
src/northbridge/amd/amdk8/northbridge.c
View File

@ -475,6 +475,6 @@ static void enumerate(struct chip *chip)
}
struct chip_control northbridge_amd_amdk8_control = {
.enumerate = enumerate,
.name = "AMD K8 Northbridge",
.enumerate = enumerate,
};

312
src/northbridge/amd/amdk8/raminit.c
View File

@ -124,6 +124,9 @@
#define DCH_MEMCLK_EN3 (1 << 29)
/* Function 3 */
#define MCA_NB_CONFIG 0x44
#define MNC_ECC_EN (1 << 22)
#define MNC_CHIPKILL_EN (1 << 23)
#define SCRUB_CONTROL 0x58
#define SCRUB_NONE 0
#define SCRUB_40ns 1
@ -1127,23 +1130,6 @@ static void spd_set_ram_size(const struct mem_controller *ctrl)
}
}
//BY LYH //Fill next base reg with right value
static void fill_last(unsigned long node_id,unsigned long base)
{
unsigned i;
unsigned base_reg;
base &=0xffff0000;
device_t device;
for(device = PCI_DEV(0, 0x18, 1); device <= PCI_DEV(0, 0x1f, 1); device
+= PCI_DEV(0, 1, 0)) {
for(i=node_id+1;i<=7;i++) {
base_reg=0x40+(i<<3);
pci_write_config32(device,base_reg,base);
}
}
}
//BY LYH END
static void route_dram_accesses(const struct mem_controller *ctrl,
unsigned long base_k, unsigned long limit_k)
{
@ -1177,7 +1163,12 @@ static void set_top_mem(unsigned tom_k)
{
/* Error if I don't have memory */
if (!tom_k) {
die("No memory");
set_bios_reset();
print_debug("No memory - reset");
/* enable cf9 */
pci_write_config8(PCI_DEV(0, 0x04, 3), 0x41, 0xf1);
/* reset */
outb(0x0e, 0x0cf9);
}
#if 1
@ -1204,15 +1195,102 @@ static void set_top_mem(unsigned tom_k)
wrmsr(TOP_MEM, msr);
}
static void order_dimms(const struct mem_controller *ctrl)
static unsigned long interleave_chip_selects(const struct mem_controller *ctrl)
{
unsigned long tom, tom_k, base_k;
unsigned node_id;
/* 35 - 25 */
static const uint32_t csbase_low[] = {
/* 32MB */ (1 << (13 - 4)),
/* 64MB */ (1 << (14 - 4)),
/* 128MB */ (1 << (14 - 4)),
/* 256MB */ (1 << (15 - 4)),
/* 512MB */ (1 << (15 - 4)),
/* 1GB */ (1 << (16 - 4)),
/* 2GB */ (1 << (16 - 4)),
};
uint32_t csbase_inc;
int chip_selects, index;
int bits;
int dual_channel;
unsigned common_size;
uint32_t csbase, csmask;
/* See if all of the memory chip selects are the same size
* and if so count them.
*/
chip_selects = 0;
common_size = 0;
for(index = 0; index < 8; index++) {
unsigned size;
uint32_t value;
value = pci_read_config32(ctrl->f2, DRAM_CSBASE + (index << 2));
/* Is it enabled? */
if (!(value & 1)) {
continue;
}
chip_selects++;
size = value >> 21;
if (common_size == 0) {
common_size = size;
}
/* The size differed fail */
if (common_size != size) {
return 0;
}
}
/* Chip selects can only be interleaved when there is
* more than one and their is a power of two of them.
*/
bits = log2(chip_selects);
if (((1 << bits) != chip_selects) || (bits < 1) || (bits > 3)) {
return 0;
}
/* Also we run out of address mask bits if we try and interleave 8 4GB dimms */
if ((bits == 3) && (common_size == (1 << (32 - 3)))) {
print_debug("8 4GB chip selects cannot be interleaved\r\n");
return 0;
}
/* Find the bits of csbase that we need to interleave on */
if (is_dual_channel(ctrl)) {
csbase_inc = csbase_low[log2(common_size) - 1] << 1;
} else {
csbase_inc = csbase_low[log2(common_size)];
}
/* Compute the initial values for csbase and csbask.
* In csbase just set the enable bit and the base to zero.
* In csmask set the mask bits for the size and page level interleave.
*/
csbase = 0 | 1;
csmask = (((common_size << bits) - 1) << 21);
csmask |= 0xfe00 & ~((csbase_inc << bits) - csbase_inc);
for(index = 0; index < 8; index++) {
uint32_t value;
value = pci_read_config32(ctrl->f2, DRAM_CSBASE + (index << 2));
/* Is it enabled? */
if (!(value & 1)) {
continue;
}
pci_write_config32(ctrl->f2, DRAM_CSBASE + (index << 2), csbase);
pci_write_config32(ctrl->f2, DRAM_CSMASK + (index << 2), csmask);
csbase += csbase_inc;
}
#if 1
print_debug("Interleaved\r\n");
#endif
/* Return the memory size in K */
return common_size << (15 + bits);
}
static unsigned long order_chip_selects(const struct mem_controller *ctrl)
{
unsigned long tom;
/* Compute the memory base address address */
base_k = 0;
/* Remember which registers we have used in the high 8 bits of tom */
tom = base_k >> 15;
tom = 0;
for(;;) {
/* Find the largest remaining canidate */
unsigned index, canidate;
@ -1270,8 +1348,19 @@ static void order_dimms(const struct mem_controller *ctrl)
pci_write_config32(ctrl->f2, DRAM_CSMASK + (canidate << 2), csmask);
}
tom_k = (tom & ~0xff000000) << 15;
/* Return the memory size in K */
return (tom & ~0xff000000) << 15;
}
static void order_dimms(const struct mem_controller *ctrl)
{
unsigned long tom, tom_k, base_k;
unsigned node_id;
tom_k = interleave_chip_selects(ctrl);
if (!tom_k) {
tom_k = order_chip_selects(ctrl);
}
/* Compute the memory base address */
base_k = 0;
for(node_id = 0; node_id < ctrl->node_id; node_id++) {
@ -1287,8 +1376,6 @@ static void order_dimms(const struct mem_controller *ctrl)
}
tom_k += base_k;
#if 0
print_debug("tom: ");
print_debug_hex32(tom);
print_debug("base_k: ");
print_debug_hex32(base_k);
print_debug(" tom_k: ");
@ -1296,9 +1383,6 @@ static void order_dimms(const struct mem_controller *ctrl)
print_debug("\r\n");
#endif
route_dram_accesses(ctrl, base_k, tom_k);
//BY LYH
fill_last(ctrl->node_id, tom_k<<2);
//BY LYH END
set_top_mem(tom_k);
}
@ -2063,6 +2147,10 @@ static void set_read_preamble(const struct mem_controller *ctrl, const struct me
/* 166Mhz, 7.5ns */
rdpreamble = ((7 << 1)+1);
}
else if (divisor == ((5 << 1)+0)) {
/* 200Mhz, 7ns */
rdpreamble = ((7 << 1)+0);
}
}
else {
int slots;
@ -2175,6 +2263,8 @@ static void spd_set_dram_timing(const struct mem_controller *ctrl, const struct
{
int dimms;
int i;
int rc;
init_Tref(ctrl, param);
for(i = 0; (i < 4) && ctrl->channel0[i]; i++) {
int rc;
@ -2247,13 +2337,16 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
print_debug_hex32(dcl);
print_debug("\r\n");
#endif
#warning "FIXME set the ECC type to perform"
#warning "FIXME initialize the scrub registers"
#if 1
if (dcl & DCL_DimmEccEn) {
uint32_t mnc;
print_debug("ECC enabled\r\n");
mnc = pci_read_config32(ctrl[i].f3, MCA_NB_CONFIG);
mnc |= MNC_ECC_EN;
if (dcl & DCL_128BitEn) {
mnc |= MNC_CHIPKILL_EN;
}
pci_write_config32(ctrl[i].f3, MCA_NB_CONFIG, mnc);
}
#endif
dcl |= DCL_DisDqsHys;
pci_write_config32(ctrl[i].f2, DRAM_CONFIG_LOW, dcl);
dcl &= ~DCL_DisDqsHys;
@ -2280,29 +2373,148 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
} else {
print_debug(" done\r\n");
}
#if 0
if (dcl & DCL_DimmEccEn) {
print_debug("Clearing memory: ");
loops = 0;
dcl &= ~DCL_MemClrStatus;
if (!is_cpu_pre_c0()) {
/* Wait until the automatic ram scrubber is finished */
dcl &= ~(DCL_MemClrStatus | DCL_DramEnable);
pci_write_config32(ctrl[i].f2, DRAM_CONFIG_LOW, dcl);
do {
dcl = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_LOW);
loops += 1;
if ((loops & 1023) == 0) {
print_debug(" ");
print_debug_hex32(loops);
} while(((dcl & DCL_MemClrStatus) == 0) || ((dcl & DCL_DramEnable) == 0) );
}
} while(((dcl & DCL_MemClrStatus) == 0) && (loops < TIMEOUT_LOOPS));
if (loops >= TIMEOUT_LOOPS) {
print_debug("failed\r\n");
} else {
uint32_t base, last_scrub_k, scrub_k;
uint32_t cnt,zstart,zend;
msr_t msr,msr_201;
/* First make certain the scrubber is disabled */
pci_write_config32(ctrl[i].f3, SCRUB_CONTROL,
(SCRUB_NONE << 16) | (SCRUB_NONE << 8) | (SCRUB_NONE << 0));
/* load the start and end for the memory block to clear */
msr_201 = rdmsr(0x201);
zstart = pci_read_config32(ctrl[0].f1, 0x40 + (i*8));
zend = pci_read_config32(ctrl[0].f1, 0x44 + (i*8));
zstart >>= 16;
zend >>=16;
#if 1
print_debug("addr ");
print_debug_hex32(zstart);
print_debug("-");
print_debug_hex32(zend);
print_debug("\r\n");
#endif
/* Disable fixed mtrrs */
msr = rdmsr(MTRRdefType_MSR);
msr.lo &= ~(1<<10);
wrmsr(MTRRdefType_MSR, msr);
/* turn on the wrap 32 disable */
msr = rdmsr(0xc0010015);
msr.lo |= (1<<17);
wrmsr(0xc0010015,msr);
for(;zstart<zend;zstart+=4) {
/* test for the last 64 meg of 4 gig space */
if(zstart == 0x0fc)
continue;
/* disable cache */
__asm__ volatile(
"movl %%cr0, %0\n\t"
"orl $0x40000000, %0\n\t"
"movl %0, %%cr0\n\t"
:"=r" (cnt)
);
/* Set the variable mtrrs to write combine */
msr.lo = 1 + ((zstart&0x0ff)<<24);
msr.hi = (zstart&0x0ff00)>>8;
wrmsr(0x200,msr);
/* Set the limit to 64 meg of ram */
msr.hi = 0x000000ff;
msr.lo = 0xfc000800;
wrmsr(0x201,msr);
/* enable cache */
__asm__ volatile(
"movl %%cr0, %0\n\t"
"andl $0x9fffffff, %0\n\t"
"movl %0, %%cr0\n\t"
:"=r" (cnt)
);
/* Set fs base address */
msr.lo = (zstart&0xff) << 24;
msr.hi = (zstart&0xff00) >> 8;
wrmsr(0xc0000100,msr);
print_debug_char((zstart > 0x0ff)?'+':'-');
/* clear memory 64meg */
__asm__ volatile(
"1: \n\t"
"movl %0, %%fs:(%1)\n\t"
"addl $4,%1\n\t"
"subl $1,%2\n\t"
"jnz 1b\n\t"
:
: "a" (0), "D" (0), "c" (0x01000000)
);
}
/* disable cache */
__asm__ volatile(
"movl %%cr0, %0\n\t"
"orl $0x40000000, %0\n\t"
"movl %0, %%cr0\n\t"
:"=r" (cnt)
);
/* restore msr registers */
msr = rdmsr(MTRRdefType_MSR);
msr.lo |= 0x0400;
wrmsr(MTRRdefType_MSR, msr);
/* Restore the variable mtrrs */
msr.lo = 6;
msr.hi = 0;
wrmsr(0x200,msr);
wrmsr(0x201,msr_201);
/* Set fs base to 0 */
msr.lo = 0;
msr.hi = 0;
wrmsr(0xc0000100,msr);
/* enable cache */
__asm__ volatile(
"movl %%cr0, %0\n\t"
"andl $0x9fffffff, %0\n\t"
"movl %0, %%cr0\n\t"
:"=r" (cnt)
);
/* turn off the wrap 32 disable */
msr = rdmsr(0xc0010015);
msr.lo &= ~(1<<17);
wrmsr(0xc0010015,msr);
/* Find the Srub base address for this cpu */
base = pci_read_config32(ctrl[i].f1, 0x40 + (ctrl[i].node_id << 3));
base &= 0xffff0000;
/* Set the scrub base address registers */
pci_write_config32(ctrl[i].f3, SCRUB_ADDR_LOW, base << 8);
pci_write_config32(ctrl[i].f3, SCRUB_ADDR_HIGH, base >> 24);
/* Enable scrubbing at the lowest possible rate */
pci_write_config32(ctrl[i].f3, SCRUB_CONTROL,
(SCRUB_84ms << 16) | (SCRUB_84ms << 8) | (SCRUB_84ms << 0));
print_debug("done\r\n");
}
pci_write_config32(ctrl[i].f3, SCRUB_ADDR_LOW, 0);
pci_write_config32(ctrl[i].f3, SCRUB_ADDR_HIGH, 0);
}
#endif
}
}

8
src/northbridge/via/vt8601/northbridge.c
View File

@ -77,8 +77,7 @@ static void enumerate(struct chip *chip)
* slower than normal, ethernet drops packets).
* Apparently these registers govern some sort of bus master behavior.
*/
static void
random_fixup() {
static void random_fixup() {
device_t pcidev = dev_find_slot(0, 0);
printk_spew("VT8601 random fixup ...\n");
@ -93,8 +92,7 @@ random_fixup() {
}
}
static void
northbridge_init(struct chip *chip, enum chip_pass pass)
static void northbridge_init(struct chip *chip, enum chip_pass pass)
{
struct northbridge_via_vt8601_config *conf =
@ -119,6 +117,6 @@ northbridge_init(struct chip *chip, enum chip_pass pass)
struct chip_control northbridge_via_vt8601_control = {
.enumerate = enumerate,
enable: northbridge_init,
.enable = northbridge_init,
.name = "VIA vt8601 Northbridge",
};

11
src/pc80/vgabios.c
View File

@ -404,8 +404,8 @@ biosint(
}
void
setup_realmode_idt(void) {
void setup_realmode_idt(void)
{
extern unsigned char idthandle, end_idthandle;
int i;
struct realidt *idts = (struct realidt *) 0;
@ -587,8 +587,7 @@ pcibios(
return retval;
}
static void
vga_init(struct chip *chip, enum chip_pass pass)
static void vga_init(struct chip *chip, enum chip_pass pass)
{
struct pc80_vgabios_config *conf =
@ -613,6 +612,6 @@ static void enumerate(struct chip *chip)
struct chip_control southbridge_via_vt8231_control = {
.enumerate = enumerate,
enable: vga_init,
name: "Legacy VGA bios"
.enable = vga_init,
.name = "Legacy VGA bios"
};

4
src/southbridge/amd/amd8111/Config.lb
View File

@ -1,5 +1,9 @@
config amd8111.h
driver amd8111.o
driver amd8111_usb.o
driver amd8111_lpc.o
driver amd8111_ide.o
driver amd8111_acpi.o
driver amd8111_usb2.o
#driver amd8111_ac97.o
#driver amd8111_nic.o

56
src/southbridge/amd/amd8111/amd8111.c Normal file
View File

@ -0,0 +1,56 @@
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/chip.h>
#include "amd8111.h"
void amd8111_enable(device_t dev)
{
device_t lpc_dev;
device_t bus_dev;
unsigned index;
uint16_t reg_old, reg;
/* See if we are on the behind the amd8111 pci bridge */
bus_dev = dev->bus->dev;
if ((bus_dev->vendor == PCI_VENDOR_ID_AMD) &&
(bus_dev->device == PCI_DEVICE_ID_AMD_8111_PCI)) {
unsigned devfn;
devfn = bus_dev->path.u.pci.devfn + (1 << 3);
lpc_dev = dev_find_slot(bus_dev->bus->secondary, devfn);
index = ((dev->path.u.pci.devfn & ~7) >> 3) + 8;
} else {
unsigned devfn;
devfn = (dev->path.u.pci.devfn) & ~7;
lpc_dev = dev_find_slot(dev->bus->secondary, devfn);
index = dev->path.u.pci.devfn & 7;
}
if ((!lpc_dev) || (index >= 16) ||
(lpc_dev->vendor != PCI_VENDOR_ID_AMD) ||
(lpc_dev->device != PCI_DEVICE_ID_AMD_8111_ISA)) {
return;
}
reg = reg_old = pci_read_config16(lpc_dev, 0x48);
reg &= ~(1 << index);
if (dev->enable) {
reg |= (1 << index);
}
if (reg != reg_old) {
#if 1
printk_warning("amd8111_enable dev: %s", dev_path(dev));
printk_warning(" lpc_dev: %s index: %d reg: %04x -> %04x ",
dev_path(lpc_dev), index, reg_old, reg);
#endif
pci_write_config16(lpc_dev, 0x48, reg);
#if 1
printk_warning("done\n");
#endif
}
}
struct chip_control southbridge_amd_amd8111_control = {
.name = "AMD 8111",
.enable_dev = amd8111_enable,
};

12
src/southbridge/amd/amd8111/amd8111.h Normal file
View File

@ -0,0 +1,12 @@
#ifndef AMD8111_H
#define AMD8111_H
struct southbridge_amd_amd8111_config
{
};
struct chip_control;
extern struct chip_control southbridge_amd_amd8111_control;
void amd8111_enable(device_t dev);
#endif /* AMD8111_H */

41
src/southbridge/amd/amd8111/amd8111_ac97.c Normal file
View File

@ -0,0 +1,41 @@
/*
* (C) 2003 Linux Networx
*/
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
#include "amd8111.h"
static struct device_operations ac97audio_ops = {
.read_resources = pci_dev_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
.enable = amd8111_enable,
.init = 0,
.scan_bus = 0,
};
static struct pci_driver ac97audio_driver __pci_driver = {
.ops = &ac97audio_ops,
.vendor = PCI_VENDOR_ID_AMD,
.device = 0x746D,
};
static struct device_operations ac97modem_ops = {
.read_resources = pci_dev_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
.enable = amd8111_enable,
.init = 0,
.scan_bus = 0,
};
static struct pci_driver ac97modem_driver __pci_driver = {
.ops = &ac97modem_ops,
.vendor = PCI_VENDOR_ID_AMD,
.device = 0x746E,
};

22
src/southbridge/amd/amd8111/amd8111_acpi.c
View File

@ -3,11 +3,23 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
#include <pc80/mc146818rtc.h>
#include "amd8111.h"
#define PREVIOUS_POWER_STATE 0x43
#define MAINBOARD_POWER_OFF 0
#define MAINBOARD_POWER_ON 1
#ifndef MAINBOARD_POWER_ON_AFTER_POWER_FAIL
#define MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON
#endif
static void acpi_init(struct device *dev)
{
uint8_t byte;
uint16_t word;
int on;
#if 0
printk_debug("ACPI: disabling NMI watchdog.. ");
@ -35,6 +47,15 @@ static void acpi_init(struct device *dev)
pci_write_config_dword(dev, 0x60, 0x06800000);
printk_debug("done.\n");
#endif
on = MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
get_option(&on, "power_on_after_fail");
byte = pci_read_config8(dev, PREVIOUS_POWER_STATE);
byte &= ~0x40;
if (!on) {
byte |= 0x40;
}
pci_write_config8(dev, PREVIOUS_POWER_STATE, byte);
printk_info("set power %s after power fail\n", on?"on":"off");
}
@ -44,6 +65,7 @@ static struct device_operations acpi_ops = {
.enable_resources = pci_dev_enable_resources,
.init = acpi_init,
.scan_bus = 0,
.enable = amd8111_enable,
};
static struct pci_driver acpi_driver __pci_driver = {

14
src/southbridge/amd/amd8111/amd8111_early_smbus.c
View File

@ -21,6 +21,8 @@ static void enable_smbus(void)
pci_write_config32(dev, 0x58, SMBUS_IO_BASE | 1);
enable = pci_read_config8(dev, 0x41);
pci_write_config8(dev, 0x41, enable | (1 << 7));
/* clear any lingering errors, so the transaction will run */
outw(inw(SMBUS_IO_BASE + SMBGSTATUS), SMBUS_IO_BASE + SMBGSTATUS);
}
@ -40,8 +42,12 @@ static int smbus_wait_until_ready(void)
if ((val & 0x800) == 0) {
break;
}
if(loops == (SMBUS_TIMEOUT / 2)) {
outw(inw(SMBUS_IO_BASE + SMBGSTATUS),
SMBUS_IO_BASE + SMBGSTATUS);
}
} while(--loops);
return loops?0:-1;
return loops?0:-2;
}
static int smbus_wait_until_done(void)
@ -57,7 +63,7 @@ static int smbus_wait_until_done(void)
break;
}
} while(--loops);
return loops?0:-1;
return loops?0:-3;
}
static int smbus_read_byte(unsigned device, unsigned address)
@ -67,7 +73,7 @@ static int smbus_read_byte(unsigned device, unsigned address)
unsigned char byte;
if (smbus_wait_until_ready() < 0) {
return -1;
return -2;
}
/* setup transaction */
@ -93,7 +99,7 @@ static int smbus_read_byte(unsigned device, unsigned address)
/* poll for transaction completion */
if (smbus_wait_until_done() < 0) {
return -1;
return -3;
}
global_status_register = inw(SMBUS_IO_BASE + SMBGSTATUS);

1
src/southbridge/amd/amd8111/amd8111_ide.c
View File

@ -3,6 +3,7 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
#include "amd8111.h"
static void ide_init(struct device *dev)
{

16
src/southbridge/amd/amd8111/amd8111_lpc.c
View File

@ -6,6 +6,8 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
#include <device/chip.h>
#include "amd8111.h"
struct ioapicreg {
@ -87,7 +89,6 @@ static void setup_ioapic(void)
static void lpc_init(struct device *dev)
{
uint8_t byte;
uint16_t word;
int pwr_on=-1;
printk_debug("lpc_init\n");
@ -102,13 +103,6 @@ static void lpc_init(struct device *dev)
byte = pci_read_config8(dev, 0x46);
pci_write_config8(dev, 0x46, byte | (1<<0));
//BY LYH
/* Disable AC97 and Ethernet */
word = pci_read_config16(dev, 0x48);
pci_write_config16(dev, 0x48, word & ~((1<<5)|(1<<6)|(1<<9)));
//BY LYH END
/* power after power fail */
byte = pci_read_config8(dev, 0x43);
if (pwr_on) {
@ -118,6 +112,10 @@ static void lpc_init(struct device *dev)
}
pci_write_config8(dev, 0x43, byte);
/* Enable Port 92 fast reset */
byte = pci_read_config8(dev, 0x41);
byte |= (1 << 5);
pci_write_config8(dev, 0x41, byte);
}
@ -159,6 +157,7 @@ static struct device_operations lpc_ops = {
.enable_resources = pci_dev_enable_resources,
.init = lpc_init,
.scan_bus = walk_static_devices,
.enable = amd8111_enable,
};
static struct pci_driver lpc_driver __pci_driver = {
@ -166,3 +165,4 @@ static struct pci_driver lpc_driver __pci_driver = {
.vendor = PCI_VENDOR_ID_AMD,
.device = PCI_DEVICE_ID_AMD_8111_ISA,
};

25
src/southbridge/amd/amd8111/amd8111_nic.c Normal file
View File

@ -0,0 +1,25 @@
/*
* (C) 2003 Linux Networx
*/
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
#include "amd8111.h"
static struct device_operations nic_ops = {
.read_resources = pci_dev_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
.enable = amd8111_enable,
.init = 0,
.scan_bus = 0,
};
static struct pci_driver nic_driver __pci_driver = {
.ops = &nic_ops,
.vendor = PCI_VENDOR_ID_AMD,
.device = 0x7462,
};

2
src/southbridge/amd/amd8111/amd8111_usb.c
View File

@ -3,6 +3,7 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
#include "amd8111.h"
static void usb_init(struct device *dev)
{
@ -25,6 +26,7 @@ static struct device_operations usb_ops = {
.enable_resources = pci_dev_enable_resources,
.init = usb_init,
.scan_bus = 0,
.enable = amd8111_enable,
};
static struct pci_driver usb_driver __pci_driver = {

7
src/southbridge/amd/amd8111/amd8111_usb2.c
View File

@ -7,6 +7,7 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
#include "amd8111.h"
static void usb2_init(struct device *dev)
{
@ -23,17 +24,17 @@ static void usb2_init(struct device *dev)
}
static struct device_operations usb_ops = {
static struct device_operations usb2_ops = {
.read_resources = pci_dev_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
.init = usb2_init,
.scan_bus = 0,
.enable = amd8111_enable,
};
static struct pci_driver usb2_driver __pci_driver = {
.ops = &usb_ops,
.ops = &usb2_ops,
.vendor = PCI_VENDOR_ID_AMD,
.device = PCI_DEVICE_ID_AMD_8111_USB2,
};

19
src/southbridge/amd/amd8131/amd8131_bridge.c
View File

@ -30,6 +30,17 @@ static void pcix_init(device_t dev)
word = 0x0404;
pci_write_config16(dev, 0xe8, word);
/* Set discard unrequested prefetch data */
word = pci_read_config16(dev, 0x4c);
word |= 1;
pci_write_config16(dev, 0x4c, word);
/* Set split transaction limits */
word = pci_read_config16(dev, 0xa8);
pci_write_config16(dev, 0xaa, word);
word = pci_read_config16(dev, 0xac);
pci_write_config16(dev, 0xae, word);
return;
}
@ -58,14 +69,6 @@ static void ioapic_enable(device_t dev)
value &= ~((1 << 1) | (1 << 0));
}
pci_write_config32(dev, 0x44, value);
//BY LYH
value = pci_read_config32(dev, 0x4);
value |= 6;
pci_write_config32(dev, 0x4, value);
//BY LYH END
}
static struct device_operations ioapic_ops = {

44
src/southbridge/via/vt8231/vt8231.c
View File

@ -11,25 +11,21 @@
void pc_keyboard_init(void);
void
hard_reset() {
void hard_reset(void)
{
printk_err("NO HARD RESET ON VT8231! FIX ME!\n");
}
static void usb_on(int enable)
{
unsigned char regval;
/* Base 8231 controller */
device_t dev0 = dev_find_device(PCI_VENDOR_ID_VIA, \
PCI_DEVICE_ID_VIA_8231, 0);
device_t dev0 = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, 0);
/* USB controller 1 */
device_t dev2 = dev_find_device(PCI_VENDOR_ID_VIA, \
PCI_DEVICE_ID_VIA_82C586_2, 0);
device_t dev2 = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_2, 0);
/* USB controller 2 */
device_t dev3 = dev_find_device(PCI_VENDOR_ID_VIA, \
PCI_DEVICE_ID_VIA_82C586_2, \
dev2);
device_t dev3 = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_2, dev2);
/* enable USB1 */
if(dev2) {
@ -70,16 +66,14 @@ static void usb_on(int enable)
regval |= 0x20;
pci_write_config8(dev0, 0x50, regval);
}
}
static void keyboard_on()
static void keyboard_on(void)
{
unsigned char regval;
/* Base 8231 controller */
device_t dev0 = dev_find_device(PCI_VENDOR_ID_VIA, \
PCI_DEVICE_ID_VIA_8231, 0);
device_t dev0 = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, 0);
/* kevinh/Ispiri - update entire function to use
new pci_write_config8 */
@ -90,10 +84,9 @@ static void keyboard_on()
pci_write_config8(dev0, 0x51, regval);
}
pc_keyboard_init();
}
static void nvram_on()
static void nvram_on(void)
{
/*
* the VIA 8231 South has a very different nvram setup than the
@ -145,7 +138,8 @@ static void ethernet_fixup()
* (e.g. device_t). This needs to get fixed. We need low-level pci scans
* in the C code.
*/
static void vt8231_pci_enable(struct southbridge_via_vt8231_config *conf) {
static void vt8231_pci_enable(struct southbridge_via_vt8231_config *conf)
{
/*
unsigned long busdevfn = 0x8000;
if (conf->enable_ide) {
@ -204,7 +198,8 @@ static void pci_routing_fixup(void)
void
dump_south(void){
dump_south(void)
{
device_t dev0;
dev0 = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, 0);
int i,j;
@ -232,11 +227,9 @@ static void vt8231_init(struct southbridge_via_vt8231_config *conf)
/* Base 8231 controller */
dev0 = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, 0);
/* IDE controller */
dev1 = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_1, \
0);
dev1 = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_1, 0);
/* Power management controller */
devpwr = dev_find_device(PCI_VENDOR_ID_VIA, \
PCI_DEVICE_ID_VIA_8231_4, 0);
devpwr = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231_4, 0);
// enable the internal I/O decode
enables = pci_read_config8(dev0, 0x6C);
@ -431,8 +424,7 @@ static void vt8231_init(struct southbridge_via_vt8231_config *conf)
rtc_init(0);
}
static void
southbridge_init(struct chip *chip, enum chip_pass pass)
static void southbridge_init(struct chip *chip, enum chip_pass pass)
{
struct southbridge_via_vt8231_config *conf =
@ -469,6 +461,6 @@ static void enumerate(struct chip *chip)
struct chip_control southbridge_via_vt8231_control = {
.enumerate = enumerate,
enable: southbridge_init,
name: "VIA vt8231"
.enable = southbridge_init,
.name = "VIA vt8231"
};

17
src/southbridge/via/vt8231/vt8231_early_serial.c
View File

@ -8,19 +8,19 @@
#define SIO_BASE 0x3f0
#define SIO_DATA SIO_BASE+1
static void
vt8231_writesuper(uint8_t reg, uint8_t val) {
static void vt8231_writesuper(uint8_t reg, uint8_t val)
{
outb(reg, SIO_BASE);
outb(val, SIO_DATA);
}
static void
vt8231_writesiobyte(uint16_t reg, uint8_t val) {
static void vt8231_writesiobyte(uint16_t reg, uint8_t val)
{
outb(val, reg);
}
static void
vt8231_writesioword(uint16_t reg, uint16_t val) {
static void vt8231_writesioword(uint16_t reg, uint16_t val)
{
outw(val, reg);
}
@ -29,8 +29,8 @@ vt8231_writesioword(uint16_t reg, uint16_t val) {
mainboard
*/
static void
enable_vt8231_serial(void) {
static void enable_vt8231_serial(void)
{
unsigned long x;
uint8_t c;
device_t dev;
@ -72,5 +72,4 @@ enable_vt8231_serial(void) {
vt8231_writesiobyte(0x3f9, 0xf);
// should be done. Dump a char for fun.
vt8231_writesiobyte(0x3f8, 48);
}

9
src/superio/NSC/pc87360/superio.c
View File

@ -306,6 +306,15 @@ static void enumerate(struct chip *chip)
resource->flags = IORESOURCE_IRQ | IORESOURCE_FIXED | IORESOURCE_SET;
}
/* Process the hard codes for the keyboard controller */
path.u.pnp.device = KBC_DEVICE;
dev = alloc_find_dev(dev, &path);
resource = get_resource(dev, 0x60);
resource->base = 0x60;
resource->flags = IORESOURCE_IO | IORESOURCE_FIXED | IORESOURCE_SET;
resource = get_resource(dev, 0x62);
resource->base = 0x64;
resource->flags = IORESOURCE_IO | IORESOURCE_FIXED | IORESOURCE_SET;
}
struct chip_control superio_NSC_pc87360_control = {

6
targets/arima/hdama/Config.lb
View File

@ -93,9 +93,7 @@ romimage "normal"
option ROM_IMAGE_SIZE=0x10000
option LINUXBIOS_EXTRA_VERSION=".0Normal"
mainboard arima/hdama
payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf
# use this to test a build if you don't have the etherboot
# payload /etc/hosts
payload /usr/share/etherboot/5.2.1eb1-lnxi-lb/tg3--ide_disk.zelf
end
romimage "fallback"
@ -103,7 +101,7 @@ romimage "fallback"
option ROM_IMAGE_SIZE=0x10000
option LINUXBIOS_EXTRA_VERSION=".0Fallback"
mainboard arima/hdama
payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf
payload /usr/share/etherboot/5.2.1eb1-lnxi-lb/tg3--ide_disk.zelf
# use this to test a build if you don't have the etherboot
# payload /etc/hosts
end

18
targets/buildtarget
View File

@ -1,5 +1,5 @@
#!/bin/sh
PYTHON=python
# Target build script
if [ $# -lt 1 ]; then
@ -17,7 +17,9 @@ fi
target_dir=$lbpath/targets
config_lb=$1
config_dir=$lbpath/util/newconfig
config_py=$config_dir/config.py
yapps2_py=$config_dir/yapps2.py
config_g=$config_dir/config.g
config_py=$config_lb/config.py
if [ ! -d $target_dir ]; then
echo "Target directory not found"
@ -38,18 +40,12 @@ fi
if [ ! -f $config_py ]; then
echo "No linuxbios config script found. Rebuilding it.."
(
cd $config_dir
make config.py
)
echo "done."
# exit 1
$PYTHON $yapps2_py $config_g $config_py
fi
# make sure config.py is up-to-date
(cd $config_dir && make config.py)
python $config_py $config_lb $lbpath
export PYTHONPATH=$config_dir
$PYTHON $config_py $config_lb $lbpath
exit $?

1
util/newconfig/Makefile
View File

@ -29,4 +29,3 @@ DISTRIB:
clean:
rm -f config.py yappsrt.pyc parsedesc.py

56
util/newconfig/config.g
View File

@ -580,7 +580,7 @@ class option_value:
class partobj:
"""A configuration part"""
def __init__ (self, image, dir, parent, part, type_name, instance_name):
def __init__ (self, image, dir, parent, part, type_name, instance_name, link):
debug.info(debug.object, "partobj dir %s parent %s part %s" \
% (dir, parent, part))
@ -627,6 +627,11 @@ class partobj:
# Path to the device
self.path = ""
# Link from parent device
if ((link < 0) or (link > 2)):
fatal("Invalid link")
self.link = link
# If no instance name is supplied then generate
# a unique name
if (instance_name == 0):
@ -704,6 +709,7 @@ class partobj:
else:
file.write("struct chip static_root = {\n")
file.write("\t/* %s %s */\n" % (self.part, self.dir))
file.write("\t.link = %d,\n" % (self.link))
if (self.path != ""):
file.write("\t.path = { %s\n\t},\n" % (self.path) );
if (self.siblings):
@ -749,33 +755,29 @@ class partobj:
value = dequote(value)
setdict(self.registercode, field, value)
def addpcipath(self, enable, channel, slot, function):
def addpcipath(self, enable, bus, slot, function):
""" Add a relative pci style path from our parent to this device """
if (channel < 0):
fatal("Invalid channel")
if ((bus < 0) or (bus > 255)):
fatal("Invalid bus")
if ((slot < 0) or (slot > 0x1f)):
fatal("Invalid device id")
if ((function < 0) or (function > 7)):
fatal("Invalid function")
self.path = "%s\n\t\t{ .channel = %d, .enable = %d, .path = {.type=DEVICE_PATH_PCI,.u={.pci={ .devfn = PCI_DEVFN(0x%x,%d) }}}}," % (self.path, channel, enable, slot, function)
self.path = "%s\n\t\t{ .enable = %d, .path = {.type=DEVICE_PATH_PCI,.u={.pci={ .bus = 0x%x, .devfn = PCI_DEVFN(0x%x,%d) }}}}," % (self.path, enable, bus, slot, function)
def addpnppath(self, enable, channel, port, device):
def addpnppath(self, enable, port, device):
""" Add a relative path to a pnp device hanging off our parent """
if (channel < 0):
fatal("Invalid channel")
if ((port < 0) or (port > 65536)):
fatal("Invalid port")
if ((device < 0) or (device > 0xff)):
fatal("Invalid device")
self.path = "%s\n\t\t{ .channel = %d, .enable = %d, .path={.type=DEVICE_PATH_PNP,.u={.pnp={ .port = 0x%x, .device = 0x%x }}}}," % (self.path, channel, enable, port, device)
self.path = "%s\n\t\t{ .enable = %d, .path={.type=DEVICE_PATH_PNP,.u={.pnp={ .port = 0x%x, .device = 0x%x }}}}," % (self.path, enable, port, device)
def addi2cpath(self, enable, channel, device):
def addi2cpath(self, enable, device):
""" Add a relative path to a i2c device hanging off our parent """
if (channel < 0):
fatal("Invalid channel")
if ((device < 0) or (device > 0x7f)):
fatal("Invalid device")
self.path = "%s\n\t\t{ .channel = %d, .enable = %d, .path = {.type=DEVICE_PATH_I2C,.u={.i2c={ .device = 0x%x }}}}, " % (self.path, channel, enable, device)
self.path = "%s\n\t\t{ .enable = %d, .path = {.type=DEVICE_PATH_I2C,.u={.i2c={ .device = 0x%x }}}}, " % (self.path, enable, device)
def usesoption(self, name):
"""Declare option that can be used by this part"""
@ -1076,7 +1078,7 @@ def mainboard(path):
setoption('MAINBOARD_VENDOR', vendor)
setoption('MAINBOARD_PART_NUMBER', part_number)
dodir('/config', 'Config.lb')
part('mainboard', path, 'Config.lb', 0)
part('mainboard', path, 'Config.lb', 0, 0)
curimage.setroot(partstack.tos())
partpop()
@ -1117,14 +1119,14 @@ def cpudir(path):
dodir(srcdir, "Config.lb")
cpu_type = path
def part(type, path, file, name):
def part(type, path, file, name, link):
global curimage, dirstack, partstack
partdir = os.path.join(type, path)
srcdir = os.path.join(treetop, 'src')
fulldir = os.path.join(srcdir, partdir)
type_name = flatten_name(os.path.join(type, path))
newpart = partobj(curimage, fulldir, partstack.tos(), type, \
type_name, name)
type_name, name, link)
print "Configuring PART %s, path %s" % (type, path)
partstack.push(newpart)
dirstack.push(fulldir)
@ -1196,7 +1198,7 @@ def setarch(my_arch):
global curimage
curimage.setarch(my_arch)
setoption('ARCH', my_arch)
part('arch', my_arch, 'Config.lb', 0)
part('arch', my_arch, 'Config.lb', 0, 0)
def doconfigfile(path, confdir, file, rule):
rname = os.path.join(confdir, file)
@ -1328,6 +1330,7 @@ parser Config:
token PCI: 'pci'
token PNP: 'pnp'
token I2C: 'i2c'
token LINK: 'link'
rule expr: logical {{ l = logical }}
@ -1371,10 +1374,11 @@ parser Config:
| SOUTHBRIDGE {{ return 'southbridge' }}
| CPU {{ return 'cpu' }}
rule partdef<<C>>: {{ name = 0 }}
rule partdef<<C>>: {{ name = 0 }} {{ link = 0 }}
parttype partid
[ STR {{ name = dequote(STR) }}
] {{ if (C): part(parttype, partid, 'Config.lb', name) }}
][ LINK NUM {{ link = long(NUM, 10) }}
] {{ if (C): part(parttype, partid, 'Config.lb', name, link) }}
partend<<C>>
rule arch<<C>>: ARCH ID {{ if (C): setarch(ID) }}
@ -1430,22 +1434,20 @@ parser Config:
| OFF {{ val = 0 }}
) ] {{ return val }}
rule pci<<C>>: PCI HEX_NUM {{ channel = int(HEX_NUM,16) }}
rule pci<<C>>: PCI HEX_NUM {{ bus = int(HEX_NUM,16) }}
':' HEX_NUM {{ slot = int(HEX_NUM,16) }}
'.' HEX_NUM {{ function = int(HEX_NUM, 16) }}
enable
{{ if (C): partstack.tos().addpcipath(enable, channel, slot, function) }}
{{ if (C): partstack.tos().addpcipath(enable, bus, slot, function) }}
rule pnp<<C>>: PNP HEX_NUM {{ channel = int(HEX_NUM,16) }}
':' HEX_NUM {{ port = int(HEX_NUM,16) }}
rule pnp<<C>>: PNP HEX_NUM {{ port = int(HEX_NUM,16) }}
'.' HEX_NUM {{ device = int(HEX_NUM, 16) }}
enable
{{ if (C): partstack.tos().addpnppath(enable, channel, port, device) }}
{{ if (C): partstack.tos().addpnppath(enable, port, device) }}
rule i2c<<C>>: I2C HEX_NUM {{ channel = int(HEX_NUM, 16) }}
':' HEX_NUM {{ device = int(HEX_NUM, 16) }}
rule i2c<<C>>: I2C HEX_NUM {{ device = int(HEX_NUM, 16) }}
enable
{{ if (C): partstatck.tos().addi2cpath(enable, channel, device) }}
{{ if (C): partstatck.tos().addi2cpath(enable, device) }}
rule prtval: expr {{ return str(expr) }}
| STR {{ return STR }}

32
util/options/build_opt_tbl.c
View File

@ -23,9 +23,10 @@ static unsigned char clip[9]={0,1,3,7,0x0f,0x1f,0x3f,0x7f,0xff};
output none
if there is an overlap, the routine exits, other wise it returns.
*/
void test_for_entry_overlaps(int entry_start,int entry_end)
void test_for_entry_overlaps(void *entry_start, void *entry_end)
{
long ptr;
int ptr;
char *cptr;
int buffer_bit_size;
int offset;
int byte;
@ -39,9 +40,10 @@ void test_for_entry_overlaps(int entry_start,int entry_end)
/* clear the temporary test buffer */
for(ptr=0; ptr < CMOS_IMAGE_BUFFER_SIZE; ptr++)
test[ptr]=0;
/* loop through each entry in the table testing for errors */
for(ptr=entry_start;ptr<entry_end;ptr+=ce->size) {
ce=(struct cmos_entries *)ptr;
for(cptr = entry_start; cptr < (char *)entry_end; cptr += ce->size) {
ce=(struct cmos_entries *)cptr;
/* test if entry goes past the end of the buffer */
if((ce->bit+ce->length)>buffer_bit_size) {
printf("Error - Entry %s start bit + length must be less than %d\n",
@ -75,7 +77,8 @@ void test_for_entry_overlaps(int entry_start,int entry_end)
} else {
/* test if bits overlap byte boundaries */
if(ce->length>(8-offset)) {
printf("Error - Entry %s length overlaps a byte boundry\n", ce->name);
printf("Error - Entry %s length overlaps a byte boundry\n",
ce->name);
exit(1);
}
/* test for bits previously used */
@ -158,8 +161,7 @@ int main(int argc, char **argv)
long ptr;
int cnt;
char *cptr;
long offset;
int entry_start;
void *entry_start, *entry_end;
int entries_length;
int enum_length;
int len;
@ -273,16 +275,14 @@ int main(int argc, char **argv)
}
/* put the length of the entries into the header section */
entries_length=(long)cptr;
entries_length-=(long)(cmos_table+ct->header_length);
entries_length = (cptr - (char *)&cmos_table) - ct->header_length;
/* compute the start of the enumerations section */
entry_start=(int)cmos_table;
entry_start+=ct->header_length;
offset=entry_start+entries_length;
c_enums_start=c_enums=(struct cmos_enums*)offset;
entry_start = ((char*)&cmos_table) + ct->header_length;
entry_end = ((char *)entry_start) + entries_length;
c_enums_start = c_enums = (struct cmos_enums*)entry_end;
/* test for overlaps in the entry records */
test_for_entry_overlaps(entry_start,offset);
test_for_entry_overlaps(entry_start, entry_end);
for(;enum_mode;){ /* loop to build the enumerations section */
if(fgets(line,INPUT_LINE_MAX,fp)==NULL)
@ -315,14 +315,14 @@ int main(int argc, char **argv)
if(cnt%4)
cnt+=4-(cnt%4);
/* store the record length */
c_enums->size=((long)&c_enums->text[cnt])-(long)c_enums;
c_enums->size=((char *)&c_enums->text[cnt]) - (char *)c_enums;
/* store the record type */
c_enums->tag=LB_TAG_OPTION_ENUM;
/* increment to the next record */
c_enums=(struct cmos_enums*)&c_enums->text[cnt];
}
/* save the enumerations length */
enum_length=(long)c_enums-(long)c_enums_start;
enum_length= (char *)c_enums - (char *)c_enums_start;
ct->size=ct->header_length+enum_length+entries_length;
/* Get the checksum records */

105
util/romcc/Makefile
View File

@ -1,5 +1,5 @@
VERSION:=0.34
RELEASE_DATE:=4 July 2003
VERSION:=0.36
RELEASE_DATE:=10 October 2003
PACKAGE:=romcc
@ -17,6 +17,15 @@ romcc: romcc.c Makefile
romcc_pg: romcc.c Makefile
$(CC) $(CFLAGS) $(CPROF_FLAGS) -o $@ $<
LINUX_TESTS=\
linux_test1.c \
linux_test2.c \
linux_test3.c \
linux_test4.c \
linux_test5.c \
linux_test6.c \
linux_test7.c \
TESTS=\
hello_world.c \
hello_world2.c \
@ -41,7 +50,6 @@ TESTS=\
simple_test19.c \
simple_test20.c \
simple_test21.c \
simple_test22.c \
simple_test23.c \
simple_test24.c \
simple_test25.c \
@ -49,7 +57,6 @@ TESTS=\
simple_test27.c \
simple_test28.c \
simple_test29.c \
simple_test30.c \
simple_test31.c \
simple_test32.c \
simple_test33.c \
@ -57,8 +64,6 @@ TESTS=\
simple_test35.c \
simple_test36.c \
simple_test37.c \
simple_test38.c \
simple_test39.c \
simple_test40.c \
simple_test41.c \
simple_test43.c \
@ -71,43 +76,113 @@ TESTS=\
simple_test51.c \
simple_test52.c \
simple_test53.c \
simple_test54.c \
simple_test55.c \
simple_test56.c \
simple_test59.c \
simple_test57.c \
simple_test58.c \
simple_test60.c \
simple_test61.c \
simple_test62.c \
simple_test63.c \
simple_test64.c \
simple_test65.c \
simple_test66.c \
simple_test67.c \
simple_test68.c \
raminit_test.c \
raminit_test2.c \
raminit_test3.c \
raminit_test4.c \
raminit_test5.c
raminit_test5.c \
raminit_test6.c \
$(LINUX_TESTS)
FAIL_TESTS = \
fail_test1.c \
fail_test2.c \
fail_test3.c
fail_test3.c \
fail_test4.c \
fail_test5.c \
TEST_SRCS:=$(patsubst %, tests/%, $(TESTS))
TEST_ASM:=$(patsubst %.c, tests/%.S, $(TESTS))
TEST_ASM_O:=$(patsubst %.c, tests/%.S-O, $(TESTS))
TEST_ASM_O2:=$(patsubst %.c, tests/%.S-O2, $(TESTS))
TEST_ASM_mmmx :=$(patsubst %.c, tests/%.S-mmmx, $(TESTS))
TEST_ASM_msse :=$(patsubst %.c, tests/%.S-msse, $(TESTS))
TEST_ASM_mmmx_msse:=$(patsubst %.c, tests/%.S-mmmx-msse, $(TESTS))
TEST_ASM_O_mmmx :=$(patsubst %.c, tests/%.S-O-mmmx, $(TESTS))
TEST_ASM_O_msse :=$(patsubst %.c, tests/%.S-O-msse, $(TESTS))
TEST_ASM_O_mmmx_msse:=$(patsubst %.c, tests/%.S-O-mmmx-msse, $(TESTS))
TEST_ASM_O2_mmmx :=$(patsubst %.c, tests/%.S-O2-mmmx, $(TESTS))
TEST_ASM_O2_msse :=$(patsubst %.c, tests/%.S-O2-msse, $(TESTS))
TEST_ASM_O2_mmmx_msse:=$(patsubst %.c, tests/%.S-O2-mmmx-msse, $(TESTS))
TEST_ASM_ALL:= $(TEST_ASM) $(TEST_ASM_O) $(TEST_ASM_O2) $(TEST_ASM_mmmx) $(TEST_ASM_msse) $(TEST_ASM_mmmx_msse) $(TEST_ASM_O_mmmx) $(TEST_ASM_O_msse) $(TEST_ASM_O_mmmx_msse) $(TEST_ASM_O2_mmmx) $(TEST_ASM_O2_msse) $(TEST_ASM_O2_mmmx_msse)
TEST_ASM_MOST:= $(TEST_ASM_O) $(TEST_ASM_O_mmmx) $(TEST_ASM_O_msse) $(TEST_ASM_O_mmmx_msse) $(TEST_ASM_O2) $(TEST_ASM_O2_mmmx) $(TEST_ASM_O2_msse) $(TEST_ASM_O2_mmmx_msse)
TEST_OBJ:=$(patsubst %.c, tests/%.o, $(TESTS))
TEST_ELF:=$(patsubst %.c, tests/%.elf, $(TESTS))
LINUX_ELF:=$(patsubst %.c, tests/%.elf, $(LINUX_TESTS))
LINUX_OUT:=$(patsubst %.c, tests/%.out, $(LINUX_TESTS))
FAIL_SRCS:=$(patsubst %, tests/%, $(FAIL_TESTS))
FAIL_OUT:=$(patsubst %.c, tests/%.out, $(FAIL_TESTS))
$(TEST_ASM): %.S: %.c romcc
export ALLOC_CHECK_=2; ./romcc -O -mcpu=k8 -o $@ $< > $*.debug
export ALLOC_CHECK_=2; ./romcc -o $@ $< > $*.debug
$(TEST_ASM_O): %.S-O: %.c romcc
export ALLOC_CHECK_=2; ./romcc -O -o $@ $< > $*.debug
$(TEST_ASM_O2): %.S-O2: %.c romcc
export ALLOC_CHECK_=2; ./romcc -O2 -o $@ $< > $*.debug
$(TEST_ASM_mmmx): %.S-mmmx: %.c romcc
export ALLOC_CHECK_=2; ./romcc -mmmx -o $@ $< > $*.debug
$(TEST_ASM_msse): %.S-msse: %.c romcc
export ALLOC_CHECK_=2; ./romcc -msse -o $@ $< > $*.debug
$(TEST_ASM_mmmx_msse): %.S-mmmx-msse: %.c romcc
export ALLOC_CHECK_=2; ./romcc -mmmx -msse -o $@ $< > $*.debug
$(TEST_ASM_O_mmmx): %.S-O-mmmx: %.c romcc
export ALLOC_CHECK_=2; ./romcc -O -mmmx -o $@ $< > $*.debug
$(TEST_ASM_O_msse): %.S-O-msse: %.c romcc
export ALLOC_CHECK_=2; ./romcc -O -msse -o $@ $< > $*.debug
$(TEST_ASM_O_mmmx_msse): %.S-O-mmmx-msse: %.c romcc
export ALLOC_CHECK_=2; ./romcc -O -mmmx -msse -o $@ $< > $*.debug
$(TEST_ASM_O2_mmmx): %.S-O2-mmmx: %.c romcc
export ALLOC_CHECK_=2; ./romcc -O2 -mmmx -o $@ $< > $*.debug
$(TEST_ASM_O2_msse): %.S-O2-msse: %.c romcc
export ALLOC_CHECK_=2; ./romcc -O2 -msse -o $@ $< > $*.debug
$(TEST_ASM_O2_mmmx_msse): %.S-O2-mmmx-msse: %.c romcc
export ALLOC_CHECK_=2; ./romcc -O2 -mmmx -msse -o $@ $< > $*.debug
$(FAIL_OUT): %.out: %.c romcc
export ALLOC_CHECK_=2; if ./romcc -O -o $*.S $< > $*.debug 2> $@ ; then exit 1 ; else exit 0 ; fi
export ALLOC_CHECK_=2; if ./romcc -O2 -o $*.S $< > $*.debug 2> $@ ; then exit 1 ; else exit 0 ; fi
$(TEST_OBJ): %.o: %.S
$(TEST_OBJ): %.o: %.S-O2-mmmx
as $< -o $@
$(TEST_ELF): %.elf: %.o tests/ldscript.ld
ld -T tests/ldscript.ld $< -o $@
test: $(TEST_ELF) $(FAIL_OUT)
$(LINUX_OUT): %.out: %.elf
./$< > $@
test: $(TEST_ELF) $(FAIL_OUT) $(TEST_ASM_MOST)
run_linux: $(LINUX_OUT)
echo:
echo "TEST_SRCS=$(TEST_SRCS)"
@ -119,5 +194,5 @@ echo:
echo "FAIL_ASM=$(FAIL_ASM)"
clean:
rm -f romcc romcc_pg core $(TEST_ASM) $(TEST_OBJ) $(TEST_ELF) tests/*.debug tests/*.debug2 tests/*.gmon.out tests/*.out
rm -f romcc romcc_pg core $(TEST_ASM_ALL) $(TEST_OBJ) $(TEST_ELF) tests/*.debug tests/*.debug2 tests/*.gmon.out tests/*.out

BIN
util/romcc/results/linux_test1.out Normal file
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59
util/romcc/results/linux_test2.out Normal file
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@ -0,0 +1,59 @@
setting up coherent ht domain....
0000c040 <-00010101
0000c044 <-00010101
0000c048 <-00010101
0000c04c <-00010101
0000c050 <-00010101
0000c054 <-00010101
0000c058 <-00010101
0000c05c <-00010101
0000c068 <-0f00840f
0000c06c <-00000070
0000c084 <-11110020
0000c088 <-00000200
0000c094 <-00ff0000
0000c144 <-003f0000
0000c14c <-00000001
0000c154 <-00000002
0000c15c <-00000003
0000c164 <-00000004
0000c16c <-00000005
0000c174 <-00000006
0000c17c <-00000007
0000c140 <-00000003
0000c148 <-00400000
0000c150 <-00400000
0000c158 <-00400000
0000c160 <-00400000
0000c168 <-00400000
0000c170 <-00400000
0000c178 <-00400000
0000c184 <-00e1ff00
0000c18c <-00dfff00
0000c194 <-00e3ff00
0000c19c <-00000000
0000c1a4 <-00000000
0000c1ac <-00000000
0000c1b4 <-00000b00
0000c1bc <-00fe0b00
0000c180 <-00e00003
0000c188 <-00d80003
0000c190 <-00e20003
0000c198 <-00000000
0000c1a0 <-00000000
0000c1a8 <-00000000
0000c1b0 <-00000a03
0000c1b8 <-00400003
0000c1c4 <-0000d000
0000c1cc <-000ff000
0000c1d4 <-00000000
0000c1dc <-00000000
0000c1c0 <-0000d003
0000c1c8 <-00001013
0000c1d0 <-00000000
0000c1d8 <-00000000
0000c1e0 <-ff000003
0000c1e4 <-00000000
0000c1e8 <-00000000
0000c1ec <-00000000
done.

11
util/romcc/results/linux_test3.out Normal file
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@ -0,0 +1,11 @@
goto_test
i = 00
i = 01
i = 02
i = 03
i = 04
i = 05
i = 06
i = 07
i = 08
i = 09

11
util/romcc/results/linux_test4.out Normal file
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@ -0,0 +1,11 @@
cpu_socketA
.up=0002 .down=ffff .across=0001
.up=0003 .down=ffff .across=0000
.up=ffff .down=0000 .across=0003
.up=ffff .down=0001 .across=0002
cpu_socketB
.up=0002 .down=ffff .across=0001
.up=0003 .down=ffff .across=0000
.up=ffff .down=0000 .across=0003
.up=ffff .down=0001 .across=0002

34
util/romcc/results/linux_test5.out Normal file
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@ -0,0 +1,34 @@
min_cycle_time: 75 min_latency: 02
A
B
C
C
D
E
device: 00 new_cycle_time: 75 new_latency: 02
G
C
D
E
G
H
device: 00 new_cycle_time: 75 new_latency: 02
I
device: 00 min_cycle_time: 75 min_latency: 02
A
B
C
C
D
E
device: 01 new_cycle_time: 75 new_latency: 02
G
C
D
E
G
H
device: 01 new_cycle_time: 75 new_latency: 02
I
device: 01 min_cycle_time: 75 min_latency: 02
min_cycle_time: 75 min_latency: 02

2
util/romcc/results/linux_test6.out Normal file
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@ -0,0 +1,2 @@
B
Registered

32
util/romcc/results/linux_test7.out Normal file
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@ -0,0 +1,32 @@
val[00]: 0000c144 0000f8f8 00000000
val[03]: 0000c14c 0000f8f8 00000001
val[06]: 0000c154 0000f8f8 00000002
val[09]: 0000c15c 0000f8f8 00000003
val[0c]: 0000c164 0000f8f8 00000004
val[0f]: 0000c16c 0000f8f8 00000005
val[12]: 0000c174 0000f8f8 00000006
val[15]: 0000c17c 0000f8f8 00000007
val[00]: 0000c144 0000f8f8 00000000
val[03]: 0000c14c 0000f8f8 00000001
val[06]: 0000c154 0000f8f8 00000002
val[09]: 0000c15c 0000f8f8 00000003
val[0c]: 0000c164 0000f8f8 00000004
val[0f]: 0000c16c 0000f8f8 00000005
val[12]: 0000c174 0000f8f8 00000006
val[15]: 0000c17c 0000f8f8 00000007
val[00]: 0000c144 0000f8f8 00000000
val[03]: 0000c14c 0000f8f8 00000001
val[06]: 0000c154 0000f8f8 00000002
val[09]: 0000c15c 0000f8f8 00000003
val[0c]: 0000c164 0000f8f8 00000004
val[0f]: 0000c16c 0000f8f8 00000005
val[12]: 0000c174 0000f8f8 00000006
val[15]: 0000c17c 0000f8f8 00000007
val[00]: 0000c144 0000f8f8 00000000
val[03]: 0000c14c 0000f8f8 00000001
val[06]: 0000c154 0000f8f8 00000002
val[09]: 0000c15c 0000f8f8 00000003
val[0c]: 0000c164 0000f8f8 00000004
val[0f]: 0000c16c 0000f8f8 00000005
val[12]: 0000c174 0000f8f8 00000006
val[15]: 0000c17c 0000f8f8 00000007

1689
util/romcc/romcc.c
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14
util/romcc/tests/fail_test4.c Normal file
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@ -0,0 +1,14 @@
static void main(void)
{
static const int foo = 2;
switch(foo) {
case 1:
break;
case 2:
break;
case 1:
break;
default:
break;
}
}

14
util/romcc/tests/fail_test5.c Normal file
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@ -0,0 +1,14 @@
static void main(void)
{
static const int foo = 2;
switch(foo) {
case 1:
break;
default:
break;
case 2:
break;
default:
break;
}
}

136
util/romcc/tests/linux_console.h Normal file
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@ -0,0 +1,136 @@
#ifndef LINUX_CONSOLE_H
#define LINUX_CONSOLE_H
#include "linux_syscall.h"
static const char *addr_of_char(unsigned char ch)
{
static const char byte[] = {
0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f,
0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27,
0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f,
0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37,
0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f,
0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47,
0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f,
0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57,
0x58, 0x59, 0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f,
0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67,
0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f,
0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77,
0x78, 0x79, 0x7a, 0x7b, 0x7c, 0x7d, 0x7e, 0x7f,
0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87,
0x88, 0x89, 0x8a, 0x8b, 0x8c, 0x8d, 0x8e, 0x8f,
0x90, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97,
0x98, 0x99, 0x9a, 0x9b, 0x9c, 0x9d, 0x9e, 0x9f,
0xa0, 0xa1, 0xa2, 0xa3, 0xa4, 0xa5, 0xa6, 0xa7,
0xa8, 0xa9, 0xaa, 0xab, 0xac, 0xad, 0xae, 0xaf,
0xb0, 0xb1, 0xb2, 0xb3, 0xb4, 0xb5, 0xb6, 0xb7,
0xb8, 0xb9, 0xba, 0xbb, 0xbc, 0xbd, 0xbe, 0xbf,
0xc0, 0xc1, 0xc2, 0xc3, 0xc4, 0xc5, 0xc6, 0xc7,
0xc8, 0xc9, 0xca, 0xcb, 0xcc, 0xcd, 0xce, 0xcf,
0xd0, 0xd1, 0xd2, 0xd3, 0xd4, 0xd5, 0xd6, 0xd7,
0xd8, 0xd9, 0xda, 0xdb, 0xdc, 0xdd, 0xde, 0xdf,
0xe0, 0xe1, 0xe2, 0xe3, 0xe4, 0xe5, 0xe6, 0xe7,
0xe8, 0xe9, 0xea, 0xeb, 0xec, 0xed, 0xee, 0xef,
0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7,
0xf8, 0xf9, 0xfa, 0xfb, 0xfc, 0xfd, 0xfe, 0xff,
};
return byte + ch;
}
static void console_tx_byte(unsigned char ch)
{
write(STDOUT_FILENO, addr_of_char(ch), 1);
}
static void console_tx_nibble(unsigned nibble)
{
unsigned char digit;
digit = nibble + '0';
if (digit > '9') {
digit += 39;
}
console_tx_byte(digit);
}
static void console_tx_char(unsigned char byte)
{
console_tx_byte(byte);
}
static void console_tx_hex8(unsigned char value)
{
console_tx_nibble((value >> 4U) & 0x0fU);
console_tx_nibble(value & 0x0fU);
}
static void console_tx_hex16(unsigned short value)
{
console_tx_nibble((value >> 12U) & 0x0FU);
console_tx_nibble((value >> 8U) & 0x0FU);
console_tx_nibble((value >> 4U) & 0x0FU);
console_tx_nibble(value & 0x0FU);
}
static void console_tx_hex32(unsigned short value)
{
console_tx_nibble((value >> 28U) & 0x0FU);
console_tx_nibble((value >> 24U) & 0x0FU);
console_tx_nibble((value >> 20U) & 0x0FU);
console_tx_nibble((value >> 16U) & 0x0FU);
console_tx_nibble((value >> 12U) & 0x0FU);
console_tx_nibble((value >> 8U) & 0x0FU);
console_tx_nibble((value >> 4U) & 0x0FU);
console_tx_nibble(value & 0x0FU);
}
static void console_tx_string(const char *str)
{
unsigned char ch;
while((ch = *str++) != '\0') {
console_tx_byte(ch);
}
}
static void print_emerg_char(unsigned char byte) { console_tx_char(byte); }
static void print_emerg_hex8(unsigned char value) { console_tx_hex8(value); }
static void print_emerg_hex16(unsigned short value){ console_tx_hex16(value); }
static void print_emerg_hex32(unsigned int value) { console_tx_hex32(value); }
static void print_emerg(const char *str) { console_tx_string(str); }
static void print_warn_char(unsigned char byte) { console_tx_char(byte); }
static void print_warn_hex8(unsigned char value) { console_tx_hex8(value); }
static void print_warn_hex16(unsigned short value){ console_tx_hex16(value); }
static void print_warn_hex32(unsigned int value) { console_tx_hex32(value); }
static void print_warn(const char *str) { console_tx_string(str); }
static void print_info_char(unsigned char byte) { console_tx_char(byte); }
static void print_info_hex8(unsigned char value) { console_tx_hex8(value); }
static void print_info_hex16(unsigned short value){ console_tx_hex16(value); }
static void print_info_hex32(unsigned int value) { console_tx_hex32(value); }
static void print_info(const char *str) { console_tx_string(str); }
static void print_debug_char(unsigned char byte) { console_tx_char(byte); }
static void print_debug_hex8(unsigned char value) { console_tx_hex8(value); }
static void print_debug_hex16(unsigned short value){ console_tx_hex16(value); }
static void print_debug_hex32(unsigned int value) { console_tx_hex32(value); }
static void print_debug(const char *str) { console_tx_string(str); }
static void print_spew_char(unsigned char byte) { console_tx_char(byte); }
static void print_spew_hex8(unsigned char value) { console_tx_hex8(value); }
static void print_spew_hex16(unsigned short value){ console_tx_hex16(value); }
static void print_spew_hex32(unsigned int value) { console_tx_hex32(value); }
static void print_spew(const char *str) { console_tx_string(str); }
static void die(const char *str)
{
print_emerg(str);
do {
asm volatile (" ");
} while(1);
}
#endif /* LINUX_CONSOLE_H */

7
util/romcc/tests/linux_syscall.h Normal file
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@ -0,0 +1,7 @@
#ifndef LINUX_SYSCALL_H
#define LINUX_SYSCALL_H
/* When I support other platforms use #ifdefs here */
#include "linuxi386_syscall.h"
#endif /* LINUX_SYSCALL_H */

8
util/romcc/tests/linux_test1.c Normal file
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@ -0,0 +1,8 @@
#include "linux_syscall.h"
static void main(void)
{
static const char msg[] = "hello world\r\n";
write(STDOUT_FILENO, msg, sizeof(msg));
_exit(0);
}

673
util/romcc/tests/linux_test2.c Normal file
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@ -0,0 +1,673 @@
#include "linux_syscall.h"
#include "linux_console.h"
static void setup_coherent_ht_domain(void)
{
static const unsigned int register_values[] = {
#if 1
( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((0x40) & 0xFF)), 0xfff0f0f0, 0x00010101,
( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((0x44) & 0xFF)), 0xfff0f0f0, 0x00010101,
( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((0x48) & 0xFF)), 0xfff0f0f0, 0x00010101,
( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((0x4c) & 0xFF)), 0xfff0f0f0, 0x00010101,
( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((0x50) & 0xFF)), 0xfff0f0f0, 0x00010101,
( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((0x54) & 0xFF)), 0xfff0f0f0, 0x00010101,
( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((0x58) & 0xFF)), 0xfff0f0f0, 0x00010101,
( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((0x5c) & 0xFF)), 0xfff0f0f0, 0x00010101,
( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((0x68) & 0xFF)), 0x00800000, 0x0f00840f,
( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((0x6C) & 0xFF)), 0xffffff8c, 0x00000000 | (1 << 6) |(1 << 5)| (1 << 4),
( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((0x84) & 0xFF)), 0x00009c05, 0x11110020,
( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((0x88) & 0xFF)), 0xfffff0ff, 0x00000200,
( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((0x94) & 0xFF)), 0xff000000, 0x00ff0000,
( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x44) & 0xFF)), 0x0000f8f8, 0x003f0000,
( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x4C) & 0xFF)), 0x0000f8f8, 0x00000001,
( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x54) & 0xFF)), 0x0000f8f8, 0x00000002,
( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x5C) & 0xFF)), 0x0000f8f8, 0x00000003,
( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x64) & 0xFF)), 0x0000f8f8, 0x00000004,
( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x6C) & 0xFF)), 0x0000f8f8, 0x00000005,
( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x74) & 0xFF)), 0x0000f8f8, 0x00000006,
( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x7C) & 0xFF)), 0x0000f8f8, 0x00000007,
( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x40) & 0xFF)), 0x0000f8fc, 0x00000003,
( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x48) & 0xFF)), 0x0000f8fc, 0x00400000,
( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x50) & 0xFF)), 0x0000f8fc, 0x00400000,
( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x58) & 0xFF)), 0x0000f8fc, 0x00400000,
( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x60) & 0xFF)), 0x0000f8fc, 0x00400000,
( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x68) & 0xFF)), 0x0000f8fc, 0x00400000,
( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x70) & 0xFF)), 0x0000f8fc, 0x00400000,
( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x78) & 0xFF)), 0x0000f8fc, 0x00400000,
( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x84) & 0xFF)), 0x00000048, 0x00e1ff00,
( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x8C) & 0xFF)), 0x00000048, 0x00dfff00,
( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x94) & 0xFF)), 0x00000048, 0x00e3ff00,
( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x9C) & 0xFF)), 0x00000048, 0x00000000,
( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xA4) & 0xFF)), 0x00000048, 0x00000000,
( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xAC) & 0xFF)), 0x00000048, 0x00000000,
( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xB4) & 0xFF)), 0x00000048, 0x00000b00,
( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xBC) & 0xFF)), 0x00000048, 0x00fe0b00,
( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x80) & 0xFF)), 0x000000f0, 0x00e00003,
( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x88) & 0xFF)), 0x000000f0, 0x00d80003,
( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x90) & 0xFF)), 0x000000f0, 0x00e20003,
( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x98) & 0xFF)), 0x000000f0, 0x00000000,
( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xA0) & 0xFF)), 0x000000f0, 0x00000000,
( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xA8) & 0xFF)), 0x000000f0, 0x00000000,
( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xB0) & 0xFF)), 0x000000f0, 0x00000a03,
( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xB8) & 0xFF)), 0x000000f0, 0x00400003,
( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xC4) & 0xFF)), 0xFE000FC8, 0x0000d000,
( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xCC) & 0xFF)), 0xFE000FC8, 0x000ff000,
( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xD4) & 0xFF)), 0xFE000FC8, 0x00000000,
( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xDC) & 0xFF)), 0xFE000FC8, 0x00000000,
( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xC0) & 0xFF)), 0xFE000FCC, 0x0000d003,
( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xC8) & 0xFF)), 0xFE000FCC, 0x00001013,
( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xD0) & 0xFF)), 0xFE000FCC, 0x00000000,
( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xD8) & 0xFF)), 0xFE000FCC, 0x00000000,
( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xE0) & 0xFF)), 0x0000FC88, 0xff000003,
( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xE4) & 0xFF)), 0x0000FC88, 0x00000000,
( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xE8) & 0xFF)), 0x0000FC88, 0x00000000,
( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xEC) & 0xFF)), 0x0000FC88, 0x00000000,
#else
#define PCI_ADDR(BUS, DEV, FN, WHERE) ( \
(((BUS) & 0xFF) << 16) | \
(((DEV) & 0x1f) << 11) | \
(((FN) & 0x07) << 8) | \
((WHERE) & 0xFF))
/* Routing Table Node i
* F0:0x40 i = 0,
* F0:0x44 i = 1,
* F0:0x48 i = 2,
* F0:0x4c i = 3,
* F0:0x50 i = 4,
* F0:0x54 i = 5,
* F0:0x58 i = 6,
* F0:0x5c i = 7
* [ 0: 3] Request Route
* [0] Route to this node
* [1] Route to Link 0
* [2] Route to Link 1
* [3] Route to Link 2
* [11: 8] Response Route
* [0] Route to this node
* [1] Route to Link 0
* [2] Route to Link 1
* [3] Route to Link 2
* [19:16] Broadcast route
* [0] Route to this node
* [1] Route to Link 0
* [2] Route to Link 1
* [3] Route to Link 2
*/
PCI_ADDR(0, 0x18, 0, 0x40), 0xfff0f0f0, 0x00010101,
PCI_ADDR(0, 0x18, 0, 0x44), 0xfff0f0f0, 0x00010101,
PCI_ADDR(0, 0x18, 0, 0x48), 0xfff0f0f0, 0x00010101,
PCI_ADDR(0, 0x18, 0, 0x4c), 0xfff0f0f0, 0x00010101,
PCI_ADDR(0, 0x18, 0, 0x50), 0xfff0f0f0, 0x00010101,
PCI_ADDR(0, 0x18, 0, 0x54), 0xfff0f0f0, 0x00010101,
PCI_ADDR(0, 0x18, 0, 0x58), 0xfff0f0f0, 0x00010101,
PCI_ADDR(0, 0x18, 0, 0x5c), 0xfff0f0f0, 0x00010101,
/* Hypetransport Transaction Control Register
* F0:0x68
* [ 0: 0] Disable read byte probe
* 0 = Probes issues
* 1 = Probes not issued
* [ 1: 1] Disable Read Doubleword probe
* 0 = Probes issued
* 1 = Probes not issued
* [ 2: 2] Disable write byte probes
* 0 = Probes issued
* 1 = Probes not issued
* [ 3: 3] Disable Write Doubleword Probes
* 0 = Probes issued
* 1 = Probes not issued.
* [ 4: 4] Disable Memroy Controller Target Start
* 0 = TgtStart packets are generated
* 1 = TgtStart packets are not generated.
* [ 5: 5] CPU1 Enable
* 0 = Second CPU disabled or not present
* 1 = Second CPU enabled.
* [ 6: 6] CPU Request PassPW
* 0 = CPU requests do not pass posted writes
* 1 = CPU requests pass posted writes.
* [ 7: 7] CPU read Respons PassPW
* 0 = CPU Responses do not pass posted writes
* 1 = CPU responses pass posted writes.
* [ 8: 8] Disable Probe Memory Cancel
* 0 = Probes may generate MemCancels
* 1 = Probes may not generate MemCancels
* [ 9: 9] Disable Remote Probe Memory Cancel.
* 0 = Probes hitting dirty blocks generate memory cancel packets
* 1 = Only probed caches on the same node as the memory controller
* generate cancel packets.
* [10:10] Disable Fill Probe
* 0 = Probes issued for cache fills
* 1 = Probes not issued for cache fills.
* [11:11] Response PassPw
* 0 = Downstream response PassPW based on original request
* 1 = Downstream response PassPW set to 1
* [12:12] Change ISOC to Ordered
* 0 = Bit 1 of coherent HT RdSz/WrSz command used for iosynchronous prioritization
* 1 = Bit 1 of coherent HT RdSz/WrSz command used for ordering.
* [14:13] Buffer Release Priority select
* 00 = 64
* 01 = 16
* 10 = 8
* 11 = 2
* [15:15] Limit Coherent HT Configuration Space Range
* 0 = No coherent HT configuration space restrictions
* 1 = Limit coherent HT configuration space based on node count
* [16:16] Local Interrupt Conversion Enable.
* 0 = ExtInt/NMI interrups unaffected.
* 1 = ExtInt/NMI broadcat interrupts converted to LINT0/1
* [17:17] APIC Extended Broadcast Enable.
* 0 = APIC broadcast is 0F
* 1 = APIC broadcast is FF
* [18:18] APIC Extended ID Enable
* 0 = APIC ID is 4 bits.
* 1 = APIC ID is 8 bits.
* [19:19] APIC Extended Spurious Vector Enable
* 0 = Lower 4 bits of spurious vector are read-only 1111
* 1 = Lower 4 bits of spurious vecotr are writeable.
* [20:20] Sequence ID Source Node Enable
* 0 = Normal operation
* 1 = Keep SeqID on routed packets for debugging.
* [22:21] Downstream non-posted request limit
* 00 = No limit
* 01 = Limited to 1
* 10 = Limited to 4
* 11 = Limited to 8
* [23:23] RESERVED
* [25:24] Medium-Priority Bypass Count
* - Maximum # of times a medium priority access can pass a low
* priority access before Medium-Priority mode is disabled for one access.
* [27:26] High-Priority Bypass Count
* - Maximum # of times a high prioirty access can pass a medium or low
* priority access before High-prioirty mode is disabled for one access.
* [28:28] Enable High Priority CPU Reads
* 0 = Cpu reads are medium prioirty
* 1 = Cpu reads are high prioirty
* [29:29] Disable Low Priority Writes
* 0 = Non-isochronous writes are low priority
* 1 = Non-isochronous writes are medium prioirty
* [30:30] Disable High Priority Isochronous writes
* 0 = Isochronous writes are high priority
* 1 = Isochronous writes are medium priority
* [31:31] Disable Medium Priority Isochronous writes
* 0 = Isochronous writes are medium are high
* 1 = With bit 30 set makes Isochrouns writes low priority.
*/
PCI_ADDR(0, 0x18, 0, 0x68), 0x00800000, 0x0f00840f,
/* HT Initialization Control Register
* F0:0x6C
* [ 0: 0] Routing Table Disable
* 0 = Packets are routed according to routing tables
* 1 = Packets are routed according to the default link field
* [ 1: 1] Request Disable (BSP should clear this)
* 0 = Request packets may be generated
* 1 = Request packets may not be generated.
* [ 3: 2] Default Link (Read-only)
* 00 = LDT0
* 01 = LDT1
* 10 = LDT2
* 11 = CPU on same node
* [ 4: 4] Cold Reset
* - Scratch bit cleared by a cold reset
* [ 5: 5] BIOS Reset Detect
* - Scratch bit cleared by a cold reset
* [ 6: 6] INIT Detect
* - Scratch bit cleared by a warm or cold reset not by an INIT
*
*/
PCI_ADDR(0, 0x18, 0, 0x6C), 0xffffff8c, 0x00000000 | (1 << 6) |(1 << 5)| (1 << 4),
/* LDTi Capabilities Registers
* F0:0x80 i = 0,
* F0:0xA0 i = 1,
* F0:0xC0 i = 2,
*/
/* LDTi Link Control Registrs
* F0:0x84 i = 0,
* F0:0xA4 i = 1,
* F0:0xC4 i = 2,
* [ 1: 1] CRC Flood Enable
* 0 = Do not generate sync packets on CRC error
* 1 = Generate sync packets on CRC error
* [ 2: 2] CRC Start Test (Read-Only)
* [ 3: 3] CRC Force Frame Error
* 0 = Do not generate bad CRC
* 1 = Generate bad CRC
* [ 4: 4] Link Failure
* 0 = No link failure detected
* 1 = Link failure detected
* [ 5: 5] Initialization Complete
* 0 = Initialization not complete
* 1 = Initialization complete
* [ 6: 6] Receiver off
* 0 = Recevier on
* 1 = Receiver off
* [ 7: 7] Transmitter Off
* 0 = Transmitter on
* 1 = Transmitter off
* [ 9: 8] CRC_Error
* 00 = No error
* [0] = 1 Error on byte lane 0
* [1] = 1 Error on byte lane 1
* [12:12] Isochrnous Enable (Read-Only)
* [13:13] HT Stop Tristate Enable
* 0 = Driven during an LDTSTOP_L
* 1 = Tristated during and LDTSTOP_L
* [14:14] Extended CTL Time
* 0 = CTL is asserted for 16 bit times during link initialization
* 1 = CTL is asserted for 50us during link initialization
* [18:16] Max Link Width In (Read-Only?)
* 000 = 8 bit link
* 001 = 16bit link
* [19:19] Doubleword Flow Control in (Read-Only)
* 0 = This link does not support doubleword flow control
* 1 = This link supports doubleword flow control
* [22:20] Max Link Width Out (Read-Only?)
* 000 = 8 bit link
* 001 = 16bit link
* [23:23] Doubleworld Flow Control out (Read-Only)
* 0 = This link does not support doubleword flow control
* 1 = This link supports doubleworkd flow control
* [26:24] Link Width In
* 000 = Use 8 bits
* 001 = Use 16 bits
* 010 = reserved
* 011 = Use 32 bits
* 100 = Use 2 bits
* 101 = Use 4 bits
* 110 = reserved
* 111 = Link physically not connected
* [27:27] Doubleword Flow Control In Enable
* 0 = Doubleword flow control disabled
* 1 = Doubleword flow control enabled (Not currently supported)
* [30:28] Link Width Out
* 000 = Use 8 bits
* 001 = Use 16 bits
* 010 = reserved
* 011 = Use 32 bits
* 100 = Use 2 bits
* 101 = Use 4 bits
* 110 = reserved
* 111 = Link physically not connected
* [31:31] Doubleworld Flow Control Out Enable
* 0 = Doubleworld flow control disabled
* 1 = Doubleword flow control enabled (Not currently supported)
*/
PCI_ADDR(0, 0x18, 0, 0x84), 0x00009c05, 0x11110020,
/* LDTi Frequency/Revision Registers
* F0:0x88 i = 0,
* F0:0xA8 i = 1,
* F0:0xC8 i = 2,
* [ 4: 0] Minor Revision
* Contains the HT Minor revision
* [ 7: 5] Major Revision
* Contains the HT Major revision
* [11: 8] Link Frequency (Takes effect the next time the link is reconnected)
* 0000 = 200Mhz
* 0001 = reserved
* 0010 = 400Mhz
* 0011 = reserved
* 0100 = 600Mhz
* 0101 = 800Mhz
* 0110 = 1000Mhz
* 0111 = reserved
* 1000 = reserved
* 1001 = reserved
* 1010 = reserved
* 1011 = reserved
* 1100 = reserved
* 1101 = reserved
* 1110 = reserved
* 1111 = 100 Mhz
* [15:12] Error (Not currently Implemented)
* [31:16] Indicates the frequency capabilities of the link
* [16] = 1 encoding 0000 of freq supported
* [17] = 1 encoding 0001 of freq supported
* [18] = 1 encoding 0010 of freq supported
* [19] = 1 encoding 0011 of freq supported
* [20] = 1 encoding 0100 of freq supported
* [21] = 1 encoding 0101 of freq supported
* [22] = 1 encoding 0110 of freq supported
* [23] = 1 encoding 0111 of freq supported
* [24] = 1 encoding 1000 of freq supported
* [25] = 1 encoding 1001 of freq supported
* [26] = 1 encoding 1010 of freq supported
* [27] = 1 encoding 1011 of freq supported
* [28] = 1 encoding 1100 of freq supported
* [29] = 1 encoding 1101 of freq supported
* [30] = 1 encoding 1110 of freq supported
* [31] = 1 encoding 1111 of freq supported
*/
PCI_ADDR(0, 0x18, 0, 0x88), 0xfffff0ff, 0x00000200,
/* LDTi Feature Capability
* F0:0x8C i = 0,
* F0:0xAC i = 1,
* F0:0xCC i = 2,
*/
/* LDTi Buffer Count Registers
* F0:0x90 i = 0,
* F0:0xB0 i = 1,
* F0:0xD0 i = 2,
*/
/* LDTi Bus Number Registers
* F0:0x94 i = 0,
* F0:0xB4 i = 1,
* F0:0xD4 i = 2,
* For NonCoherent HT specifies the bus number downstream (behind the host bridge)
* [ 0: 7] Primary Bus Number
* [15: 8] Secondary Bus Number
* [23:15] Subordiante Bus Number
* [31:24] reserved
*/
PCI_ADDR(0, 0x18, 0, 0x94), 0xff000000, 0x00ff0000,
/* LDTi Type Registers
* F0:0x98 i = 0,
* F0:0xB8 i = 1,
* F0:0xD8 i = 2,
*/
/* Careful set limit registers before base registers which contain the enables */
/* DRAM Limit i Registers
* F1:0x44 i = 0
* F1:0x4C i = 1
* F1:0x54 i = 2
* F1:0x5C i = 3
* F1:0x64 i = 4
* F1:0x6C i = 5
* F1:0x74 i = 6
* F1:0x7C i = 7
* [ 2: 0] Destination Node ID
* 000 = Node 0
* 001 = Node 1
* 010 = Node 2
* 011 = Node 3
* 100 = Node 4
* 101 = Node 5
* 110 = Node 6
* 111 = Node 7
* [ 7: 3] Reserved
* [10: 8] Interleave select
* specifies the values of A[14:12] to use with interleave enable.
* [15:11] Reserved
* [31:16] DRAM Limit Address i Bits 39-24
* This field defines the upper address bits of a 40 bit address
* that define the end of the DRAM region.
*/
#if MEMORY_1024MB
PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x003f0000,
#endif
#if MEMORY_512MB
PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x001f0000,
#endif
PCI_ADDR(0, 0x18, 1, 0x4C), 0x0000f8f8, 0x00000001,
PCI_ADDR(0, 0x18, 1, 0x54), 0x0000f8f8, 0x00000002,
PCI_ADDR(0, 0x18, 1, 0x5C), 0x0000f8f8, 0x00000003,
PCI_ADDR(0, 0x18, 1, 0x64), 0x0000f8f8, 0x00000004,
PCI_ADDR(0, 0x18, 1, 0x6C), 0x0000f8f8, 0x00000005,
PCI_ADDR(0, 0x18, 1, 0x74), 0x0000f8f8, 0x00000006,
PCI_ADDR(0, 0x18, 1, 0x7C), 0x0000f8f8, 0x00000007,
/* DRAM Base i Registers
* F1:0x40 i = 0
* F1:0x48 i = 1
* F1:0x50 i = 2
* F1:0x58 i = 3
* F1:0x60 i = 4
* F1:0x68 i = 5
* F1:0x70 i = 6
* F1:0x78 i = 7
* [ 0: 0] Read Enable
* 0 = Reads Disabled
* 1 = Reads Enabled
* [ 1: 1] Write Enable
* 0 = Writes Disabled
* 1 = Writes Enabled
* [ 7: 2] Reserved
* [10: 8] Interleave Enable
* 000 = No interleave
* 001 = Interleave on A[12] (2 nodes)
* 010 = reserved
* 011 = Interleave on A[12] and A[14] (4 nodes)
* 100 = reserved
* 101 = reserved
* 110 = reserved
* 111 = Interleve on A[12] and A[13] and A[14] (8 nodes)
* [15:11] Reserved
* [13:16] DRAM Base Address i Bits 39-24
* This field defines the upper address bits of a 40-bit address
* that define the start of the DRAM region.
*/
PCI_ADDR(0, 0x18, 1, 0x40), 0x0000f8fc, 0x00000003,
#if MEMORY_1024MB
PCI_ADDR(0, 0x18, 1, 0x48), 0x0000f8fc, 0x00400000,
PCI_ADDR(0, 0x18, 1, 0x50), 0x0000f8fc, 0x00400000,
PCI_ADDR(0, 0x18, 1, 0x58), 0x0000f8fc, 0x00400000,
PCI_ADDR(0, 0x18, 1, 0x60), 0x0000f8fc, 0x00400000,
PCI_ADDR(0, 0x18, 1, 0x68), 0x0000f8fc, 0x00400000,
PCI_ADDR(0, 0x18, 1, 0x70), 0x0000f8fc, 0x00400000,
PCI_ADDR(0, 0x18, 1, 0x78), 0x0000f8fc, 0x00400000,
#endif
#if MEMORY_512MB
PCI_ADDR(0, 0x18, 1, 0x48), 0x0000f8fc, 0x00200000,
PCI_ADDR(0, 0x18, 1, 0x50), 0x0000f8fc, 0x00200000,
PCI_ADDR(0, 0x18, 1, 0x58), 0x0000f8fc, 0x00200000,
PCI_ADDR(0, 0x18, 1, 0x60), 0x0000f8fc, 0x00200000,
PCI_ADDR(0, 0x18, 1, 0x68), 0x0000f8fc, 0x00200000,
PCI_ADDR(0, 0x18, 1, 0x70), 0x0000f8fc, 0x00200000,
PCI_ADDR(0, 0x18, 1, 0x78), 0x0000f8fc, 0x00200000,
#endif
/* Memory-Mapped I/O Limit i Registers
* F1:0x84 i = 0
* F1:0x8C i = 1
* F1:0x94 i = 2
* F1:0x9C i = 3
* F1:0xA4 i = 4
* F1:0xAC i = 5
* F1:0xB4 i = 6
* F1:0xBC i = 7
* [ 2: 0] Destination Node ID
* 000 = Node 0
* 001 = Node 1
* 010 = Node 2
* 011 = Node 3
* 100 = Node 4
* 101 = Node 5
* 110 = Node 6
* 111 = Node 7
* [ 3: 3] Reserved
* [ 5: 4] Destination Link ID
* 00 = Link 0
* 01 = Link 1
* 10 = Link 2
* 11 = Reserved
* [ 6: 6] Reserved
* [ 7: 7] Non-Posted
* 0 = CPU writes may be posted
* 1 = CPU writes must be non-posted
* [31: 8] Memory-Mapped I/O Limit Address i (39-16)
* This field defines the upp adddress bits of a 40-bit address that
* defines the end of a memory-mapped I/O region n
*/
PCI_ADDR(0, 0x18, 1, 0x84), 0x00000048, 0x00e1ff00,
PCI_ADDR(0, 0x18, 1, 0x8C), 0x00000048, 0x00dfff00,
PCI_ADDR(0, 0x18, 1, 0x94), 0x00000048, 0x00e3ff00,
PCI_ADDR(0, 0x18, 1, 0x9C), 0x00000048, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xA4), 0x00000048, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xAC), 0x00000048, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xB4), 0x00000048, 0x00000b00,
PCI_ADDR(0, 0x18, 1, 0xBC), 0x00000048, 0x00fe0b00,
/* Memory-Mapped I/O Base i Registers
* F1:0x80 i = 0
* F1:0x88 i = 1
* F1:0x90 i = 2
* F1:0x98 i = 3
* F1:0xA0 i = 4
* F1:0xA8 i = 5
* F1:0xB0 i = 6
* F1:0xB8 i = 7
* [ 0: 0] Read Enable
* 0 = Reads disabled
* 1 = Reads Enabled
* [ 1: 1] Write Enable
* 0 = Writes disabled
* 1 = Writes Enabled
* [ 2: 2] Cpu Disable
* 0 = Cpu can use this I/O range
* 1 = Cpu requests do not use this I/O range
* [ 3: 3] Lock
* 0 = base/limit registers i are read/write
* 1 = base/limit registers i are read-only
* [ 7: 4] Reserved
* [31: 8] Memory-Mapped I/O Base Address i (39-16)
* This field defines the upper address bits of a 40bit address
* that defines the start of memory-mapped I/O region i
*/
PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00e00003,
PCI_ADDR(0, 0x18, 1, 0x88), 0x000000f0, 0x00d80003,
PCI_ADDR(0, 0x18, 1, 0x90), 0x000000f0, 0x00e20003,
PCI_ADDR(0, 0x18, 1, 0x98), 0x000000f0, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xA0), 0x000000f0, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xA8), 0x000000f0, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xB0), 0x000000f0, 0x00000a03,
#if MEMORY_1024MB
PCI_ADDR(0, 0x18, 1, 0xB8), 0x000000f0, 0x00400003,
#endif
#if MEMORY_512MB
PCI_ADDR(0, 0x18, 1, 0xB8), 0x000000f0, 0x00200003,
#endif
/* PCI I/O Limit i Registers
* F1:0xC4 i = 0
* F1:0xCC i = 1
* F1:0xD4 i = 2
* F1:0xDC i = 3
* [ 2: 0] Destination Node ID
* 000 = Node 0
* 001 = Node 1
* 010 = Node 2
* 011 = Node 3
* 100 = Node 4
* 101 = Node 5
* 110 = Node 6
* 111 = Node 7
* [ 3: 3] Reserved
* [ 5: 4] Destination Link ID
* 00 = Link 0
* 01 = Link 1
* 10 = Link 2
* 11 = reserved
* [11: 6] Reserved
* [24:12] PCI I/O Limit Address i
* This field defines the end of PCI I/O region n
* [31:25] Reserved
*/
PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x0000d000,
PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x000ff000,
PCI_ADDR(0, 0x18, 1, 0xD4), 0xFE000FC8, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xDC), 0xFE000FC8, 0x00000000,
/* PCI I/O Base i Registers
* F1:0xC0 i = 0
* F1:0xC8 i = 1
* F1:0xD0 i = 2
* F1:0xD8 i = 3
* [ 0: 0] Read Enable
* 0 = Reads Disabled
* 1 = Reads Enabled
* [ 1: 1] Write Enable
* 0 = Writes Disabled
* 1 = Writes Enabled
* [ 3: 2] Reserved
* [ 4: 4] VGA Enable
* 0 = VGA matches Disabled
* 1 = matches all address < 64K and where A[9:0] is in the
* range 3B0-3BB or 3C0-3DF independen of the base & limit registers
* [ 5: 5] ISA Enable
* 0 = ISA matches Disabled
* 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block
* from matching agains this base/limit pair
* [11: 6] Reserved
* [24:12] PCI I/O Base i
* This field defines the start of PCI I/O region n
* [31:25] Reserved
*/
PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x0000d003,
PCI_ADDR(0, 0x18, 1, 0xC8), 0xFE000FCC, 0x00001013,
PCI_ADDR(0, 0x18, 1, 0xD0), 0xFE000FCC, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xD8), 0xFE000FCC, 0x00000000,
/* Config Base and Limit i Registers
* F1:0xE0 i = 0
* F1:0xE4 i = 1
* F1:0xE8 i = 2
* F1:0xEC i = 3
* [ 0: 0] Read Enable
* 0 = Reads Disabled
* 1 = Reads Enabled
* [ 1: 1] Write Enable
* 0 = Writes Disabled
* 1 = Writes Enabled
* [ 2: 2] Device Number Compare Enable
* 0 = The ranges are based on bus number
* 1 = The ranges are ranges of devices on bus 0
* [ 3: 3] Reserved
* [ 6: 4] Destination Node
* 000 = Node 0
* 001 = Node 1
* 010 = Node 2
* 011 = Node 3
* 100 = Node 4
* 101 = Node 5
* 110 = Node 6
* 111 = Node 7
* [ 7: 7] Reserved
* [ 9: 8] Destination Link
* 00 = Link 0
* 01 = Link 1
* 10 = Link 2
* 11 - Reserved
* [15:10] Reserved
* [23:16] Bus Number Base i
* This field defines the lowest bus number in configuration region i
* [31:24] Bus Number Limit i
* This field defines the highest bus number in configuration regin i
*/
PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0xff000003,
PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000,
#endif
};
int i;
int max;
print_debug("setting up coherent ht domain....\r\n");
max = sizeof(register_values)/sizeof(register_values[0]);
for(i = 0; i < max; i += 3) {
unsigned long reg;
#if 1
print_debug_hex32(register_values[i]);
print_debug(" <-");
print_debug_hex32(register_values[i+2]);
print_debug("\r\n");
#endif
#if 0
reg = pci_read_config32(register_values[i]);
reg &= register_values[i+1];
reg |= register_values[i+2] & ~register_values[i+1];
pci_write_config32(register_values[i], reg);
#endif
}
print_debug("done.\r\n");
}
static void main(void)
{
static const char msg[] = "hello world\r\n";
#if 0
write(STDOUT_FILENO, msg, sizeof(msg));
#endif
#if 1
setup_coherent_ht_domain();
#endif
_exit(0);
}

28
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#include "linux_syscall.h"
#include "linux_console.h"
static void goto_test(void)
{
int i;
print_debug("goto_test\n");
i = 0;
goto bottom;
{
top:
print_debug("i = ");
print_debug_hex8(i);
print_debug("\n");
i = i + 1;
}
bottom:
if (i < 10) {
goto top;
}
}
static void main(void)
{
goto_test();
_exit(0);
}

46
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#include "linux_syscall.h"
#include "linux_console.h"
struct socket_desc {
short up;
short down;
short across;
};
static void main(void)
{
static const struct socket_desc cpu_socketsA[] = {
{ .up = 2, .down = -1, .across = 1 }, /* Node 0 */
{ .up = 3, .down = -1, .across = 0 }, /* Node 1 */
{ .up = -1, .down = 0, .across = 3 }, /* Node 2 */
{ .up = -1, .down = 1, .across = 2 } /* Node 3 */
};
static const struct socket_desc cpu_socketsB[4] = {
{ 2, -1, 1 }, /* Node 0 */
{ 3, -1, 0 }, /* Node 1 */
{ -1, 0, 3 }, /* Node 2 */
{ -1, 1, 2 } /* Node 3 */
};
int i;
print_debug("cpu_socketA\n");
for(i = 0; i < sizeof(cpu_socketsA)/sizeof(cpu_socketsA[0]); i++) {
print_debug(".up=");
print_debug_hex16(cpu_socketsA[i].up);
print_debug(" .down=");
print_debug_hex16(cpu_socketsA[i].down);
print_debug(" .across=");
print_debug_hex16(cpu_socketsA[i].across);
print_debug("\n");
}
print_debug("\ncpu_socketB\n");
for(i = 0; i < sizeof(cpu_socketsB)/sizeof(cpu_socketsB[0]); i++) {
print_debug(".up=");
print_debug_hex16(cpu_socketsB[i].up);
print_debug(" .down=");
print_debug_hex16(cpu_socketsB[i].down);
print_debug(" .across=");
print_debug_hex16(cpu_socketsB[i].across);
print_debug("\n");
}
_exit(0);
}

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#include "linux_syscall.h"
#include "linux_console.h"
int log2(int value)
{
/* __builtin_bsr is a exactly equivalent to the x86 machine
* instruction with the exception that it returns -1
* when the value presented to it is zero.
* Otherwise __builtin_bsr returns the zero based index of
* the highest bit set.
*/
return __builtin_bsr(value);
}
static int smbus_read_byte(unsigned device, unsigned address)
{
static const unsigned char dimm[] = {
0x80, 0x08, 0x07, 0x0d, 0x0a, 0x02, 0x48, 0x00, 0x04, 0x60, 0x70, 0x02, 0x82, 0x08, 0x08, 0x01,
0x0e, 0x04, 0x0c, 0x01, 0x02, 0x20, 0x00, 0x75, 0x70, 0x00, 0x00, 0x48, 0x30, 0x48, 0x2a, 0x40,
0x80, 0x80, 0x45, 0x45, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x33,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0x80, 0x08, 0x07, 0x0d, 0x0a, 0x02, 0x48, 0x00, 0x04, 0x60, 0x70, 0x02, 0x82, 0x08, 0x08, 0x01,
0x0e, 0x04, 0x0c, 0x01, 0x02, 0x20, 0x00, 0x75, 0x70, 0x00, 0x00, 0x48, 0x30, 0x48, 0x2a, 0x40,
0x80, 0x80, 0x45, 0x45, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x33,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
};
return dimm[(device << 8) + address];
}
#define SMBUS_MEM_DEVICE_START 0x00
#define SMBUS_MEM_DEVICE_END 0x01
#define SMBUS_MEM_DEVICE_INC 1
/* Function 2 */
#define DRAM_CONFIG_HIGH 0x94
#define DCH_MEMCLK_SHIFT 20
#define DCH_MEMCLK_MASK 7
#define DCH_MEMCLK_100MHZ 0
#define DCH_MEMCLK_133MHZ 2
#define DCH_MEMCLK_166MHZ 5
#define DCH_MEMCLK_200MHZ 7
/* Function 3 */
#define NORTHBRIDGE_CAP 0xE8
#define NBCAP_128Bit 0x0001
#define NBCAP_MP 0x0002
#define NBCAP_BIG_MP 0x0004
#define NBCAP_ECC 0x0004
#define NBCAP_CHIPKILL_ECC 0x0010
#define NBCAP_MEMCLK_SHIFT 5
#define NBCAP_MEMCLK_MASK 3
#define NBCAP_MEMCLK_100MHZ 3
#define NBCAP_MEMCLK_133MHZ 2
#define NBCAP_MEMCLK_166MHZ 1
#define NBCAP_MEMCLK_200MHZ 0
#define NBCAP_MEMCTRL 0x0100
typedef unsigned char uint8_t;
typedef unsigned int uint32_t;
static unsigned spd_to_dimm(unsigned device)
{
return (device - SMBUS_MEM_DEVICE_START);
}
static void disable_dimm(unsigned index)
{
print_debug("disabling dimm");
print_debug_hex8(index);
print_debug("\r\n");
#if 0
pci_write_config32(PCI_DEV(0, 0x18, 2), DRAM_CSBASE + (((index << 1)+0)<<2), 0);
pci_write_config32(PCI_DEV(0, 0x18, 2), DRAM_CSBASE + (((index << 1)+1)<<2), 0);
#endif
}
struct mem_param {
uint8_t cycle_time;
uint32_t dch_memclk;
};
static const struct mem_param *get_mem_param(unsigned min_cycle_time)
{
static const struct mem_param speed[] = {
{
.cycle_time = 0xa0,
.dch_memclk = DCH_MEMCLK_100MHZ << DCH_MEMCLK_SHIFT,
},
{
.cycle_time = 0x75,
.dch_memclk = DCH_MEMCLK_133MHZ << DCH_MEMCLK_SHIFT,
},
{
.cycle_time = 0x60,
.dch_memclk = DCH_MEMCLK_166MHZ << DCH_MEMCLK_SHIFT,
},
{
.cycle_time = 0x50,
.dch_memclk = DCH_MEMCLK_200MHZ << DCH_MEMCLK_SHIFT,
},
{
.cycle_time = 0x00,
},
};
const struct mem_param *param;
for(param = &speed[0]; param->cycle_time ; param++) {
if (min_cycle_time > (param+1)->cycle_time) {
break;
}
}
if (!param->cycle_time) {
die("min_cycle_time to low");
}
return param;
}
#if 1
static void debug(int c)
{
print_debug_char(c);
print_debug_char('\r');
print_debug_char('\n');
}
#endif
static const struct mem_param *spd_set_memclk(void)
{
/* Compute the minimum cycle time for these dimms */
const struct mem_param *param;
unsigned min_cycle_time, min_latency;
unsigned device;
uint32_t value;
static const int latency_indicies[] = { 26, 23, 9 };
static const unsigned char min_cycle_times[] = {
[NBCAP_MEMCLK_200MHZ] = 0x50, /* 5ns */
[NBCAP_MEMCLK_166MHZ] = 0x60, /* 6ns */
[NBCAP_MEMCLK_133MHZ] = 0x75, /* 7.5ns */
[NBCAP_MEMCLK_100MHZ] = 0xa0, /* 10ns */
};
#if 0
value = pci_read_config32(PCI_DEV(0, 0x18, 3), NORTHBRIDGE_CAP);
#else
value = 0x50;
#endif
min_cycle_time = min_cycle_times[(value >> NBCAP_MEMCLK_SHIFT) & NBCAP_MEMCLK_MASK];
min_latency = 2;
#if 1
print_debug("min_cycle_time: ");
print_debug_hex8(min_cycle_time);
print_debug(" min_latency: ");
print_debug_hex8(min_latency);
print_debug("\r\n");
#endif
/* Compute the least latency with the fastest clock supported
* by both the memory controller and the dimms.
*/
for(device = SMBUS_MEM_DEVICE_START;
device <= SMBUS_MEM_DEVICE_END;
device += SMBUS_MEM_DEVICE_INC)
{
int new_cycle_time, new_latency;
int index;
int latencies;
int latency;
debug('A');
/* First find the supported CAS latencies
* Byte 18 for DDR SDRAM is interpreted:
* bit 0 == CAS Latency = 1.0
* bit 1 == CAS Latency = 1.5
* bit 2 == CAS Latency = 2.0
* bit 3 == CAS Latency = 2.5
* bit 4 == CAS Latency = 3.0
* bit 5 == CAS Latency = 3.5
* bit 6 == TBD
* bit 7 == TBD
*/
new_cycle_time = 0xa0;
new_latency = 5;
latencies = smbus_read_byte(device, 18);
if (latencies <= 0) continue;
debug('B');
/* Compute the lowest cas latency supported */
latency = log2(latencies) -2;
/* Loop through and find a fast clock with a low latency */
for(index = 0; index < 3; index++, latency++) {
int value;
debug('C');
if ((latency < 2) || (latency > 4) ||
(!(latencies & (1 << latency)))) {
continue;
}
debug('D');
value = smbus_read_byte(device, latency_indicies[index]);
if (value < 0) continue;
debug('E');
/* Only increase the latency if we decreas the clock */
if ((value >= min_cycle_time) && (value < new_cycle_time)) {
new_cycle_time = value;
new_latency = latency;
#if 1
print_debug("device: ");
print_debug_hex8(device);
print_debug(" new_cycle_time: ");
print_debug_hex8(new_cycle_time);
print_debug(" new_latency: ");
print_debug_hex8(new_latency);
print_debug("\r\n");
#endif
}
debug('G');
}
debug('H');
#if 1
print_debug("device: ");
print_debug_hex8(device);
print_debug(" new_cycle_time: ");
print_debug_hex8(new_cycle_time);
print_debug(" new_latency: ");
print_debug_hex8(new_latency);
print_debug("\r\n");
#endif
if (new_latency > 4){
continue;
}
debug('I');
/* Does min_latency need to be increased? */
if (new_cycle_time > min_cycle_time) {
min_cycle_time = new_cycle_time;
}
/* Does min_cycle_time need to be increased? */
if (new_latency > min_latency) {
min_latency = new_latency;
}
#if 1
print_debug("device: ");
print_debug_hex8(device);
print_debug(" min_cycle_time: ");
print_debug_hex8(min_cycle_time);
print_debug(" min_latency: ");
print_debug_hex8(min_latency);
print_debug("\r\n");
#endif
}
/* Make a second pass through the dimms and disable
* any that cannot support the selected memclk and cas latency.
*/
for(device = SMBUS_MEM_DEVICE_START;
device <= SMBUS_MEM_DEVICE_END;
device += SMBUS_MEM_DEVICE_INC)
{
int latencies;
int latency;
int index;
int value;
int dimm;
latencies = smbus_read_byte(device, 18);
if (latencies <= 0) {
goto dimm_err;
}
/* Compute the lowest cas latency supported */
latency = log2(latencies) -2;
/* Walk through searching for the selected latency */
for(index = 0; index < 3; index++, latency++) {
if (!(latencies & (1 << latency))) {
continue;
}
if (latency == min_latency)
break;
}
/* If I can't find the latency or my index is bad error */
if ((latency != min_latency) || (index >= 3)) {
goto dimm_err;
}
/* Read the min_cycle_time for this latency */
value = smbus_read_byte(device, latency_indicies[index]);
/* All is good if the selected clock speed
* is what I need or slower.
*/
if (value <= min_cycle_time) {
continue;
}
/* Otherwise I have an error, disable the dimm */
dimm_err:
disable_dimm(spd_to_dimm(device));
}
#if 1
print_debug("min_cycle_time: ");
print_debug_hex8(min_cycle_time);
print_debug(" min_latency: ");
print_debug_hex8(min_latency);
print_debug("\r\n");
#endif
/* Now that I know the minimum cycle time lookup the memory parameters */
param = get_mem_param(min_cycle_time);
#if 0
/* Update DRAM Config High with our selected memory speed */
value = pci_read_config32(PCI_DEV(0, 0x18, 2), DRAM_CONFIG_HIGH);
value &= ~(DCH_MEMCLK_MASK << DCH_MEMCLK_SHIFT);
value |= param->dch_memclk;
pci_write_config32(PCI_DEV(0, 0x18, 2), DRAM_CONFIG_HIGH, value);
static const unsigned latencies[] = { 1, 5, 2 };
/* Update DRAM Timing Low wiht our selected cas latency */
value = pci_read_config32(PCI_DEV(0, 0x18, 2), DRAM_CONFIG_LOW);
value &= ~7;
value |= latencies[min_latency - 2];
pci_write_config32(PCI_DEV(0, 0x18, 2), DRAM_CONFIG_LOW, value);
#endif
return param;
}
static void main(void)
{
const struct mem_param *param;
param = spd_set_memclk();
_exit(0);
}

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#include "linux_syscall.h"
#include "linux_console.h"
static void main(void)
{
static const int value[] = { 1, 0 };
const char *str;
if (value[1]) {
print_debug("A\r\n");
str = "Unbuffered\r\n";
} else {
print_debug("B\r\n");
str = "Registered\r\n";
}
print_debug(str);
_exit(0);
}

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#include "linux_syscall.h"
#include "linux_console.h"
static void main(void)
{
static const int cpu[] = { 0, 1, 2, 3 };
int i;
for(i = 0; i < sizeof(cpu)/sizeof(cpu[0]); i++) {
static const unsigned int register_values[] = {
0x0000c144, 0x0000f8f8, 0x00000000,
0x0000c14C, 0x0000f8f8, 0x00000001,
0x0000c154, 0x0000f8f8, 0x00000002,
0x0000c15C, 0x0000f8f8, 0x00000003,
0x0000c164, 0x0000f8f8, 0x00000004,
0x0000c16C, 0x0000f8f8, 0x00000005,
0x0000c174, 0x0000f8f8, 0x00000006,
0x0000c17C, 0x0000f8f8, 0x00000007,
};
int j;
int max = sizeof(register_values)/sizeof(register_values[0]);
for(j = 0; j < max; j += 3) {
print_debug("val[");
print_debug_hex8(j);
print_debug("]: ");
print_debug_hex32(register_values[j]);
print_debug_char(' ');
print_debug_hex32(register_values[j+1]);
print_debug_char(' ');
print_debug_hex32(register_values[j+2]);
print_debug_char('\n');
}
}
_exit(0);
}

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struct syscall_result {
long val;
int errno;
};
static struct syscall_result syscall_return(long result)
{
struct syscall_result res;
if (((unsigned long)result) >= ((unsigned long)-125)) {
res.errno = - result;
res.val = -1;
} else {
res.errno = 0;
res.val = result;
}
return res;
}
static struct syscall_result syscall0(unsigned long nr)
{
long res;
asm volatile(
"int $0x80"
: "=a" (res)
: "a" (nr));
return syscall_return(res);
}
static struct syscall_result syscall1(unsigned long nr, unsigned long arg1)
{
long res;
asm volatile(
"int $0x80"
: "=a" (res)
: "a" (nr), "b" (arg1));
return syscall_return(res);
}
static struct syscall_result syscall2(unsigned long nr, unsigned long arg1, unsigned long arg2)
{
long res;
asm volatile(
"int $0x80"
: "=a" (res)
: "a" (nr), "b" (arg1), "c" (arg2));
return syscall_return(res);
}
static struct syscall_result syscall3(unsigned long nr, unsigned long arg1, unsigned long arg2,
unsigned long arg3)
{
long res;
asm volatile(
"int $0x80"
: "=a" (res)
: "a" (nr), "b" (arg1), "c" (arg2), "d" (arg3));
return syscall_return(res);
}
static struct syscall_result syscall4(unsigned long nr, unsigned long arg1, unsigned long arg2,
unsigned long arg3, unsigned long arg4)
{
long res;
asm volatile(
"int $0x80"
: "=a" (res)
: "a" (nr), "b" (arg1), "c" (arg2), "d" (arg3), "S" (arg4));
return syscall_return(res);
}
static struct syscall_result syscall5(unsigned long nr, unsigned long arg1, unsigned long arg2,
unsigned long arg3, unsigned long arg4, unsigned long arg5)
{
long res;
asm volatile(
"int $0x80"
: "=a" (res)
: "a" (nr), "b" (arg1), "c" (arg2), "d" (arg3),
"S" (arg4), "D" (arg5));
return syscall_return(res);
}
#define NR_exit 1
#define NR_fork 2
#define NR_read 3
#define NR_write 4
#define NR_open 5
#define NR_close 6
#define NR_waitpid 7
#define NR_creat 8
#define NR_link 9
#define NR_unlink 10
#define NR_execve 11
#define NR_chdir 12
#define NR_time 13
#define NR_mknod 14
#define NR_chmod 15
#define NR_lchown 16
#define NR_break 17
#define NR_oldstat 18
#define NR_lseek 19
#define NR_getpid 20
#define NR_mount 21
#define NR_umount 22
#define NR_setuid 23
#define NR_getuid 24
#define NR_stime 25
#define NR_ptrace 26
#define NR_alarm 27
#define NR_oldfstat 28
#define NR_pause 29
#define NR_utime 30
#define NR_stty 31
#define NR_gtty 32
#define NR_access 33
#define NR_nice 34
#define NR_ftime 35
#define NR_sync 36
#define NR_kill 37
#define NR_rename 38
#define NR_mkdir 39
#define NR_rmdir 40
#define NR_dup 41
#define NR_pipe 42
#define NR_times 43
#define NR_prof 44
#define NR_brk 45
#define NR_setgid 46
#define NR_getgid 47
#define NR_signal 48
#define NR_geteuid 49
#define NR_getegid 50
#define NR_acct 51
#define NR_umount2 52
#define NR_lock 53
#define NR_ioctl 54
#define NR_fcntl 55
#define NR_mpx 56
#define NR_setpgid 57
#define NR_ulimit 58
#define NR_oldolduname 59
#define NR_umask 60
#define NR_chroot 61
#define NR_ustat 62
#define NR_dup2 63
#define NR_getppid 64
#define NR_getpgrp 65
#define NR_setsid 66
#define NR_sigaction 67
#define NR_sgetmask 68
#define NR_ssetmask 69
#define NR_setreuid 70
#define NR_setregid 71
#define NR_sigsuspend 72
#define NR_sigpending 73
#define NR_sethostname 74
#define NR_setrlimit 75
#define NR_getrlimit 76
#define NR_getrusage 77
#define NR_gettimeofday 78
#define NR_settimeofday 79
#define NR_getgroups 80
#define NR_setgroups 81
#define NR_select 82
#define NR_symlink 83
#define NR_oldlstat 84
#define NR_readlink 85
#define NR_uselib 86
#define NR_swapon 87
#define NR_reboot 88
#define NR_readdir 89
#define NR_mmap 90
#define NR_munmap 91
#define NR_truncate 92
#define NR_ftruncate 93
#define NR_fchmod 94
#define NR_fchown 95
#define NR_getpriority 96
#define NR_setpriority 97
#define NR_profil 98
#define NR_statfs 99
#define NR_fstatfs 100
#define NR_ioperm 101
#define NR_socketcall 102
#define NR_syslog 103
#define NR_setitimer 104
#define NR_getitimer 105
#define NR_stat 106
#define NR_lstat 107
#define NR_fstat 108
#define NR_olduname 109
#define NR_iopl 110
#define NR_vhangup 111
#define NR_idle 112
#define NR_vm86old 113
#define NR_wait4 114
#define NR_swapoff 115
#define NR_sysinfo 116
#define NR_ipc 117
#define NR_fsync 118
#define NR_sigreturn 119
#define NR_clone 120
#define NR_setdomainname 121
#define NR_uname 122
#define NR_modify_ldt 123
#define NR_adjtimex 124
#define NR_mprotect 125
#define NR_sigprocmask 126
#define NR_create_module 127
#define NR_init_module 128
#define NR_delete_module 129
#define NR_get_kernel_syms 130
#define NR_quotactl 131
#define NR_getpgid 132
#define NR_fchdir 133
#define NR_bdflush 134
#define NR_sysfs 135
#define NR_personality 136
#define NR_afs_syscall 137 /* Syscall for Andrew File System */
#define NR_setfsuid 138
#define NR_setfsgid 139
#define NR__llseek 140
#define NR_getdents 141
#define NR__newselect 142
#define NR_flock 143
#define NR_msync 144
#define NR_readv 145
#define NR_writev 146
#define NR_getsid 147
#define NR_fdatasync 148
#define NR__sysctl 149
#define NR_mlock 150
#define NR_munlock 151
#define NR_mlockall 152
#define NR_munlockall 153
#define NR_sched_setparam 154
#define NR_sched_getparam 155
#define NR_sched_setscheduler 156
#define NR_sched_getscheduler 157
#define NR_sched_yield 158
#define NR_sched_get_priority_max 159
#define NR_sched_get_priority_min 160
#define NR_sched_rr_get_interval 161
#define NR_nanosleep 162
#define NR_mremap 163
#define NR_setresuid 164
#define NR_getresuid 165
#define NR_vm86 166
#define NR_query_module 167
#define NR_poll 168
#define NR_nfsservctl 169
#define NR_setresgid 170
#define NR_getresgid 171
#define NR_prctl 172
#define NR_rt_sigreturn 173
#define NR_rt_sigaction 174
#define NR_rt_sigprocmask 175
#define NR_rt_sigpending 176
#define NR_rt_sigtimedwait 177
#define NR_rt_sigqueueinfo 178
#define NR_rt_sigsuspend 179
#define NR_pread 180
#define NR_pwrite 181
#define NR_chown 182
#define NR_getcwd 183
#define NR_capget 184
#define NR_capset 185
#define NR_sigaltstack 186
#define NR_sendfile 187
#define NR_getpmsg 188 /* some people actually want streams */
#define NR_putpmsg 189 /* some people actually want streams */
#define NR_vfork 190
/* Standard file descriptors */
#define STDIN_FILENO 0 /* Standard input */
#define STDOUT_FILENO 1 /* Standard output */
#define STDERR_FILENO 2 /* Standard error output */
typedef long ssize_t;
typedef unsigned long size_t;
static ssize_t write(int fd, const void *buf, size_t count)
{
struct syscall_result res;
res = syscall3(NR_write, fd, (unsigned long)buf, count);
return res.val;
}
static void _exit(int status)
{
struct syscall_result res;
res = syscall1(NR_exit, status);
}

2800
util/romcc/tests/raminit_test6.c Normal file
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5
util/romcc/tests/simple_test57.c Normal file
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static void main(void)
{
for(;;) {
}
}

9
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static void main(void)
{
const char *str;
unsigned char ch;
str = "one\r\n";
while((ch = *str++) != '\0') {
__builtin_outb(ch, 0x3f0);
}
}

26
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static void spd_set_nbxcfg(void)
{
/*
* Effects: Uses serial presence detect to set the
* ECC support flags in the NBXCFG register
* FIXME: Check for illegal/unsupported ram configurations and abort
*/
unsigned device;
for(device = 0x50; device <= 0x53; device += 1) {
int byte;
byte = 0; /* Disable ECC */
/* 0 == None, 1 == Parity, 2 == ECC */
if (byte != 2) continue;
/* set the device I'm talking too */
__builtin_outb(device, 0x1004);
/* poll for transaction completion */
byte = __builtin_inb(0x10);
while(byte == 0) {
byte = __builtin_inb(0x10);
}
}
}

7
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static const int foo = 1;
static void main(void)
{
int x;
x = foo;
}

8
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static const int foo[] = { 1, 2 };
static void main(void)
{
int x, y;
x = foo[0];
y = foo[1];
}

12
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static void main(void)
{
static const int foo = 2;
switch(foo) {
case 1:
break;
case 2:
break;
default:
break;
}
}

10
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enum tag {
X=1,
Y=2,
};
static void main(void)
{
enum tag foo;
foo = Y;
}

25
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typedef unsigned char uint8_t;
static unsigned int generate_row(uint8_t row, uint8_t maxnodes)
{
unsigned int ret=0x00010101;
static const unsigned int rows_2p[2][2] = {
{ 0x00050101, 0x00010404 },
{ 0x00010404, 0x00050101 }
};
if(maxnodes>2) {
maxnodes=2;
}
if (row < maxnodes) {
ret=rows_2p[0][row];
}
return ret;
}
static void setup_node(void)
{
unsigned char row;
for(row=0; row< 2; row++) {
__builtin_outl(generate_row(row, 2), 0x1234);
}
}

24
util/romcc/tests/simple_test67.c Normal file
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static void main(void)
{
unsigned int dch, dcl;
/* HERE I AM async_lat */
unsigned async_lat;
int dimms;
dimms = 1;
async_lat = 0;
dch = 0x1234;
dcl = __builtin_inl(0x5678);
if (!(dcl & (1 << 8))) {
if (dimms == 4) {
async_lat = 9;
}
else {
async_lat = 8;
}
}
else {
async_lat = 6;
}
dch |= async_lat;
__builtin_outl(dch, 0x9abc);
}

21
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static void main(void)
{
static const int cpu[] = { 0, 1, 2, 3 };
int i;
for(i = 0; i < sizeof(cpu)/sizeof(cpu[0]); i++) {
static const unsigned int register_values[] = {
0x0000c144, 0x0000f8f8, 0x00000000,
0x0000c14C, 0x0000f8f8, 0x00000001,
0x0000c154, 0x0000f8f8, 0x00000002,
0x0000c15C, 0x0000f8f8, 0x00000003,
0x0000c164, 0x0000f8f8, 0x00000004,
0x0000c16C, 0x0000f8f8, 0x00000005,
0x0000c174, 0x0000f8f8, 0x00000006,
0x0000c17C, 0x0000f8f8, 0x00000007,
};
int j;
int max = sizeof(register_values)/sizeof(register_values[0]);
for(j = 0; j < max; j += 3) {
}
}
}