device/dram/ddr3: Drop unused MRS helpers
These aren't used anywhere anymore. Change-Id: I4cf2fc0d07a772886e90fba4f66591a7b0a40e6c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47343 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
This commit is contained in:
Angel Pons
@@ -638,226 +638,3 @@ void dram_print_spd_ddr3(const struct dimm_attr_ddr3_st *dimm)
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printk(BIOS_INFO, " tCMDmin : %3u\n",
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DIV_ROUND_UP(dimm->tCMD, 256));
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}
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/*==============================================================================
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*= DDR3 MRS helpers
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*----------------------------------------------------------------------------*/
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/*
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* MRS command structure:
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* cmd[15:0] = Address pins MA[15:0]
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* cmd[18:16] = Bank address BA[2:0]
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*/
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/* Map tWR value to a bitmask of the MR0 cycle */
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static u16 ddr3_twr_to_mr0_map(u8 twr)
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{
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if ((twr >= 5) && (twr <= 8))
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return (twr - 4) << 9;
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/*
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* From 8T onwards, we can only use even values. Round up if we are
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* given an odd value.
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*/
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if ((twr >= 9) && (twr <= 14))
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return ((twr + 1) >> 1) << 9;
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/* tWR == 16T is [000] */
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return 0;
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}
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/* Map the CAS latency to a bitmask for the MR0 cycle */
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static u16 ddr3_cas_to_mr0_map(u8 cas)
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{
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u16 mask = 0;
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/* A[6:4] are bits [2:0] of (CAS - 4) */
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mask = ((cas - 4) & 0x07) << 4;
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/* A2 is the MSB of (CAS - 4) */
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if ((cas - 4) & (1 << 3))
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mask |= (1 << 2);
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return mask;
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}
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/**
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* \brief Get command address for a DDR3 MR0 command
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*
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* The DDR3 specification only covers odd write_recovery up to 7T. If an odd
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* write_recovery greater than 7 is specified, it will be rounded up. If a tWR
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* greater than 8 is specified, it is recommended to explicitly round it up or
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* down before calling this function.
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*
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* write_recovery and cas are given in clock cycles. For example, a CAS of 7T
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* should be given as 7.
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*
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* @param precharge_pd
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* @param write_recovery Write recovery latency, tWR in clock cycles.
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* @param dll_reset
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* @param mode
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* @param cas CAS latency in clock cycles.
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* @param burst_type
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* @param burst_length
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*/
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mrs_cmd_t ddr3_get_mr0(enum ddr3_mr0_precharge precharge_pd,
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u8 write_recovery,
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enum ddr3_mr0_dll_reset dll_reset,
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enum ddr3_mr0_mode mode,
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u8 cas,
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enum ddr3_mr0_burst_type burst_type,
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enum ddr3_mr0_burst_length burst_length)
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{
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mrs_cmd_t cmd = 0 << 16;
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if (precharge_pd == DDR3_MR0_PRECHARGE_FAST)
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cmd |= (1 << 12);
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cmd |= ddr3_twr_to_mr0_map(write_recovery);
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if (dll_reset == DDR3_MR0_DLL_RESET_YES)
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cmd |= (1 << 8);
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if (mode == DDR3_MR0_MODE_TEST)
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cmd |= (1 << 7);
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cmd |= ddr3_cas_to_mr0_map(cas);
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if (burst_type == DDR3_MR0_BURST_TYPE_INTERLEAVED)
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cmd |= (1 << 3);
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cmd |= (burst_length & 0x03) << 0;
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return cmd;
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}
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static u16 ddr3_rtt_nom_to_mr1_map(enum ddr3_mr1_rtt_nom rtt_nom)
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{
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u16 mask = 0;
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/* A9 <-> rtt_nom[2] */
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if (rtt_nom & (1 << 2))
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mask |= (1 << 9);
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/* A6 <-> rtt_nom[1] */
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if (rtt_nom & (1 << 1))
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mask |= (1 << 6);
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/* A2 <-> rtt_nom[0] */
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if (rtt_nom & (1 << 0))
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mask |= (1 << 2);
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return mask;
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}
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static u16 ddr3_ods_to_mr1_map(enum ddr3_mr1_ods ods)
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{
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u16 mask = 0;
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/* A5 <-> ods[1] */
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if (ods & (1 << 1))
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mask |= (1 << 5);
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/* A1 <-> ods[0] */
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if (ods & (1 << 0))
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mask |= (1 << 1);
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return mask;
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}
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/**
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* \brief Get command address for a DDR3 MR1 command
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*/
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mrs_cmd_t ddr3_get_mr1(enum ddr3_mr1_qoff qoff,
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enum ddr3_mr1_tqds tqds,
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enum ddr3_mr1_rtt_nom rtt_nom,
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enum ddr3_mr1_write_leveling write_leveling,
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enum ddr3_mr1_ods ods,
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enum ddr3_mr1_additive_latency additive_latency,
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enum ddr3_mr1_dll dll_disable)
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{
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mrs_cmd_t cmd = 1 << 16;
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if (qoff == DDR3_MR1_QOFF_DISABLE)
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cmd |= (1 << 12);
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if (tqds == DDR3_MR1_TQDS_ENABLE)
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cmd |= (1 << 11);
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cmd |= ddr3_rtt_nom_to_mr1_map(rtt_nom);
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if (write_leveling == DDR3_MR1_WRLVL_ENABLE)
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cmd |= (1 << 7);
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cmd |= ddr3_ods_to_mr1_map(ods);
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cmd |= (additive_latency & 0x03) << 3;
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if (dll_disable == DDR3_MR1_DLL_DISABLE)
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cmd |= (1 << 0);
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return cmd;
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}
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/**
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* \brief Get command address for a DDR3 MR2 command
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*
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* cas_cwl is given in clock cycles. For example, a cas_cwl of 7T should be
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* given as 7.
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*
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* @param rtt_wr
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* @param extended_temp
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* @param self_refresh
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* @param cas_cwl CAS write latency in clock cycles.
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*/
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mrs_cmd_t ddr3_get_mr2(enum ddr3_mr2_rttwr rtt_wr,
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enum ddr3_mr2_srt_range extended_temp,
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enum ddr3_mr2_asr self_refresh, u8 cas_cwl)
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{
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mrs_cmd_t cmd = 2 << 16;
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cmd |= (rtt_wr & 0x03) << 9;
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if (extended_temp == DDR3_MR2_SRT_EXTENDED)
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cmd |= (1 << 7);
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if (self_refresh == DDR3_MR2_ASR_AUTO)
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cmd |= (1 << 6);
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cmd |= ((cas_cwl - 5) & 0x07) << 3;
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return cmd;
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}
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/**
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* \brief Get command address for a DDR3 MR3 command
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*
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* @param dataflow_from_mpr Specify a non-zero value to put DRAM in read
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* leveling mode. Zero for normal operation.
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*/
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mrs_cmd_t ddr3_get_mr3(char dataflow_from_mpr)
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{
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mrs_cmd_t cmd = 3 << 16;
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if (dataflow_from_mpr)
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cmd |= (1 << 2);
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return cmd;
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}
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/**
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* \brief Mirror the address bits for this MRS command
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*
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* Swap the following bits in the MRS command:
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* - MA3 <-> MA4
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* - MA5 <-> MA6
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* - MA7 <-> MA8
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* - BA0 <-> BA1
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*/
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mrs_cmd_t ddr3_mrs_mirror_pins(mrs_cmd_t cmd)
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{
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u32 downshift, upshift;
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/* High bits= A4 | A6 | A8 | BA1 */
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/* Low bits = A3 | A5 | A7 | BA0 */
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u32 lowbits = (1 << 3) | (1 << 5) | (1 << 7) | (1 << 16);
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downshift = (cmd & (lowbits << 1));
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upshift = (cmd & lowbits);
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cmd &= ~(lowbits | (lowbits << 1));
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cmd |= (downshift >> 1) | (upshift << 1);
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return cmd;
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}
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@@ -181,135 +181,5 @@ int spd_xmp_decode_ddr3(struct dimm_attr_ddr3_st *dimm,
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enum cb_err spd_add_smbios17(const u8 channel, const u8 slot,
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const u16 selected_freq,
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const struct dimm_attr_ddr3_st *info);
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/**
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* \brief Read double word from specified address
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*
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* Should be useful when doing an MRS to the DIMM
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*/
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static inline u32 volatile_read(volatile uintptr_t addr)
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{
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volatile u32 result;
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result = *(volatile u32 *)addr;
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return result;
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}
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/**
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* \brief Representation of an MRS command
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*
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* This represents an MRS command as seen by the DIMM. This is not a memory
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* address that can be read to generate an MRS command. The mapping of CPU
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* to memory pins is hardware-dependent.
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* \n
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* The idea is to generalize the MRS code, and only need a hardware-specific
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* function to map the MRS bits to CPU address bits. An MRS command can be
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* sent like:
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* @code{.c}
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* u32 addr;
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* mrs_cmd_t mrs;
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* chipset_enable_mrs_command_mode();
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* mrs = ddr3_get_mr2(rtt_wr, srt, asr, cwl)
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* if (rank_has_mirrorred_pins)
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* mrs = ddr3_mrs_mirror_pins(mrs);
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* addr = chipset_specific_get_mrs_addr(mrs);
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* volatile_read(addr);
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* @endcode
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*
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* The MRS representation has the following structure:
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* - cmd[15:0] = Address pins MA[15:0]
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* - cmd[18:16] = Bank address BA[2:0]
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*/
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typedef u32 mrs_cmd_t;
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enum ddr3_mr0_precharge {
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DDR3_MR0_PRECHARGE_SLOW = 0,
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DDR3_MR0_PRECHARGE_FAST = 1,
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};
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enum ddr3_mr0_mode {
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DDR3_MR0_MODE_NORMAL = 0,
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DDR3_MR0_MODE_TEST = 1,
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};
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enum ddr3_mr0_dll_reset {
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DDR3_MR0_DLL_RESET_NO = 0,
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DDR3_MR0_DLL_RESET_YES = 1,
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};
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enum ddr3_mr0_burst_type {
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DDR3_MR0_BURST_TYPE_SEQUENTIAL = 0,
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DDR3_MR0_BURST_TYPE_INTERLEAVED = 1,
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};
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enum ddr3_mr0_burst_length {
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DDR3_MR0_BURST_LENGTH_8 = 0,
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DDR3_MR0_BURST_LENGTH_CHOP = 1,
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DDR3_MR0_BURST_LENGTH_4 = 2,
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};
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mrs_cmd_t ddr3_get_mr0(enum ddr3_mr0_precharge precharge_pd,
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u8 write_recovery,
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enum ddr3_mr0_dll_reset dll_reset,
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enum ddr3_mr0_mode mode,
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u8 cas,
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enum ddr3_mr0_burst_type interleaved_burst,
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enum ddr3_mr0_burst_length burst_length);
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enum ddr3_mr1_qoff {
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DDR3_MR1_QOFF_ENABLE = 0,
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DDR3_MR1_QOFF_DISABLE = 1,
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};
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enum ddr3_mr1_tqds {
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DDR3_MR1_TQDS_DISABLE = 0,
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DDR3_MR1_TQDS_ENABLE = 1,
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};
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enum ddr3_mr1_write_leveling {
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DDR3_MR1_WRLVL_DISABLE = 0,
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DDR3_MR1_WRLVL_ENABLE = 1,
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};
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enum ddr3_mr1_rtt_nom {
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DDR3_MR1_RTT_NOM_OFF = 0,
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DDR3_MR1_RTT_NOM_RZQ4 = 1,
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DDR3_MR1_RTT_NOM_RZQ2 = 2,
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DDR3_MR1_RTT_NOM_RZQ6 = 3,
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DDR3_MR1_RTT_NOM_RZQ12 = 4,
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DDR3_MR1_RTT_NOM_RZQ8 = 5,
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};
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enum ddr3_mr1_additive_latency {
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DDR3_MR1_AL_DISABLE = 0,
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DDR3_MR1_AL_CL_MINUS_1 = 1,
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DDR3_MR1_AL_CL_MINUS_2 = 2,
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};
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enum ddr3_mr1_ods {
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DDR3_MR1_ODS_RZQ6 = 0,
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DDR3_MR1_ODS_RZQ7 = 1,
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};
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enum ddr3_mr1_dll {
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DDR3_MR1_DLL_ENABLE = 0,
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DDR3_MR1_DLL_DISABLE = 1,
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};
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mrs_cmd_t ddr3_get_mr1(enum ddr3_mr1_qoff qoff,
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enum ddr3_mr1_tqds tqds,
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enum ddr3_mr1_rtt_nom rtt_nom,
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enum ddr3_mr1_write_leveling write_leveling,
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enum ddr3_mr1_ods output_drive_strenght,
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enum ddr3_mr1_additive_latency additive_latency,
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enum ddr3_mr1_dll dll_disable);
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enum ddr3_mr2_rttwr {
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DDR3_MR2_RTTWR_OFF = 0,
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DDR3_MR2_RTTWR_RZQ4 = 1,
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DDR3_MR2_RTTWR_RZQ2 = 2,
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};
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enum ddr3_mr2_srt_range {
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DDR3_MR2_SRT_NORMAL = 0,
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DDR3_MR2_SRT_EXTENDED = 1,
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};
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enum ddr3_mr2_asr {
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DDR3_MR2_ASR_MANUAL = 0,
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DDR3_MR2_ASR_AUTO = 1,
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};
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mrs_cmd_t ddr3_get_mr2(enum ddr3_mr2_rttwr rtt_wr,
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enum ddr3_mr2_srt_range extended_temp,
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enum ddr3_mr2_asr self_refresh, u8 cas_cwl);
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mrs_cmd_t ddr3_get_mr3(char dataflow_from_mpr);
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mrs_cmd_t ddr3_mrs_mirror_pins(mrs_cmd_t cmd);
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#endif /* DEVICE_DRAM_DDR3L_H */
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Reference in New Issue
Block a user