sravan/system76-coreboot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

mb/google,intel: Use common ChromeEC code for lid shutdown

Browse Source 
Change-Id: I4d34e5c094440dad4a6ab9adc67d3da6b71ac2bf
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74514
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
This commit is contained in:
Kyösti Mälkki
2023-01-05 15:39:16 +02:00
parent 923b8ec180
commit 83faa5d804
10 changed files with 56 additions and 177 deletions
Download Patch File Download Diff File Expand all files Collapse all files

32
src/mainboard/google/auron/smihandler.c
View File

@@ -1,11 +1,9 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <acpi/acpi.h>
#include <arch/io.h>
#include <console/console.h>
#include <cpu/x86/smm.h>
#include <soc/pm.h>
#include <elog.h>
#include <ec/google/chromeec/ec.h>
#include <ec/google/chromeec/smm.h>
#include <southbridge/intel/lynxpoint/lp_gpio.h>
@@ -14,37 +12,11 @@
#include "ec.h"
#include <variant/onboard.h>
static u8 mainboard_smi_ec(void)
{
u8 cmd = google_chromeec_get_event();
u32 pm1_cnt;
/* Log this event */
if (cmd)
elog_gsmi_add_event_byte(ELOG_TYPE_EC_EVENT, cmd);
switch (cmd) {
case EC_HOST_EVENT_LID_CLOSED:
printk(BIOS_DEBUG, "LID CLOSED, SHUTDOWN\n");
/* Go to S5 */
pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT);
pm1_cnt |= (0xf << 10);
outl(pm1_cnt, ACPI_BASE_ADDRESS + PM1_CNT);
break;
}
return cmd;
}
/* gpi_sts is GPIO 47:32 */
void mainboard_smi_gpi(u32 gpi_sts)
{
if (gpi_sts & (1 << (EC_SMI_GPI - 32))) {
/* Process all pending events */
while (mainboard_smi_ec() != 0)
;
}
if (gpi_sts & (1 << (EC_SMI_GPI - 32)))
chromeec_smi_process_events();
}
static void mainboard_disable_gpios(void)

33
src/mainboard/google/cyan/smihandler.c
View File

@@ -1,14 +1,12 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <acpi/acpi.h>
#include <arch/io.h>
#include <device/mmio.h>
#include <console/console.h>
#include <cpu/x86/smm.h>
#include "ec.h"
#include <ec/google/chromeec/ec.h>
#include <ec/google/chromeec/smm.h>
#include <elog.h>
#include <soc/nvs.h>
#include <soc/pm.h>
#include <soc/gpio.h>
@@ -20,41 +18,14 @@
#define GPIO_SUS7_WAKE_MASK (1 << 12)
#define GPIO_SUS1_WAKE_MASK (1 << 13)
static uint8_t mainboard_smi_ec(void)
{
uint8_t cmd = google_chromeec_get_event();
uint16_t pmbase = get_pmbase();
uint32_t pm1_cnt;
/* Log this event */
if (cmd)
elog_gsmi_add_event_byte(ELOG_TYPE_EC_EVENT, cmd);
switch (cmd) {
case EC_HOST_EVENT_LID_CLOSED:
printk(BIOS_DEBUG, "LID CLOSED, SHUTDOWN\n");
/* Go to S5 */
pm1_cnt = inl(pmbase + PM1_CNT);
pm1_cnt |= SLP_EN | (SLP_TYP_S5 << SLP_TYP_SHIFT);
outl(pm1_cnt, pmbase + PM1_CNT);
break;
}
return cmd;
}
/*
* The entire 32-bit ALT_GPIO_SMI register is passed as a parameter. Note, that
* this includes the enable bits in the lower 16 bits.
*/
void mainboard_smi_gpi(uint32_t alt_gpio_smi)
{
if (alt_gpio_smi & (1 << EC_SMI_GPI)) {
/* Process all pending events */
while (mainboard_smi_ec() != 0)
;
}
if (alt_gpio_smi & (1 << EC_SMI_GPI))
chromeec_smi_process_events();
}
void mainboard_smi_sleep(uint8_t slp_typ)

28
src/mainboard/google/link/smihandler.c
View File

@@ -6,41 +6,17 @@
#include <soc/nvs.h>
#include <southbridge/intel/bd82x6x/pch.h>
#include <southbridge/intel/bd82x6x/me.h>
#include <southbridge/intel/common/pmbase.h>
#include <northbridge/intel/sandybridge/sandybridge.h>
#include <elog.h>
/* Include EC functions */
#include <ec/google/chromeec/ec.h>
#include <ec/google/chromeec/smm.h>
#include "ec.h"
static u8 mainboard_smi_ec(void)
{
u8 cmd = google_chromeec_get_event();
/* Log this event */
if (cmd)
elog_gsmi_add_event_byte(ELOG_TYPE_EC_EVENT, cmd);
switch (cmd) {
case EC_HOST_EVENT_LID_CLOSED:
printk(BIOS_DEBUG, "LID CLOSED, SHUTDOWN\n");
/* Go to S5 */
write_pmbase32(PM1_CNT, read_pmbase32(PM1_CNT) | (0xf << 10));
break;
}
return cmd;
}
void mainboard_smi_gpi(u32 gpi_sts)
{
if (gpi_sts & (1 << EC_SMI_GPI)) {
/* Process all pending events */
while (mainboard_smi_ec() != 0);
}
if (gpi_sts & (1 << EC_SMI_GPI))
chromeec_smi_process_events();
}
void mainboard_smi_sleep(u8 slp_typ)

32
src/mainboard/google/rambi/smihandler.c
View File

@@ -1,10 +1,8 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <acpi/acpi.h>
#include <arch/io.h>
#include <console/console.h>
#include <cpu/x86/smm.h>
#include <elog.h>
#include <ec/google/chromeec/ec.h>
#include <ec/google/chromeec/smm.h>
@@ -16,38 +14,12 @@
/* The wake gpio is SUS_GPIO[0]. */
#define WAKE_GPIO_EN SUS_GPIO_EN0
static uint8_t mainboard_smi_ec(void)
{
uint8_t cmd = google_chromeec_get_event();
uint16_t pmbase = get_pmbase();
uint32_t pm1_cnt;
/* Log this event */
if (cmd)
elog_gsmi_add_event_byte(ELOG_TYPE_EC_EVENT, cmd);
switch (cmd) {
case EC_HOST_EVENT_LID_CLOSED:
printk(BIOS_DEBUG, "LID CLOSED, SHUTDOWN\n");
/* Go to S5 */
pm1_cnt = inl(pmbase + PM1_CNT);
pm1_cnt |= SLP_EN | (SLP_TYP_S5 << SLP_TYP_SHIFT);
outl(pm1_cnt, pmbase + PM1_CNT);
break;
}
return cmd;
}
/* The entire 32-bit ALT_GPIO_SMI register is passed as a parameter. Note, that
* this includes the enable bits in the lower 16 bits. */
void mainboard_smi_gpi(uint32_t alt_gpio_smi)
{
if (alt_gpio_smi & (1 << EC_SMI_GPI)) {
/* Process all pending events */
while (mainboard_smi_ec() != 0);
}
if (alt_gpio_smi & (1 << EC_SMI_GPI))
chromeec_smi_process_events();
}
void mainboard_smi_sleep(uint8_t slp_typ)

31
src/mainboard/google/slippy/smihandler.c
View File

@@ -1,7 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <acpi/acpi.h>
#include <arch/io.h>
#include <console/console.h>
#include <cpu/x86/smm.h>
#include <soc/nvs.h>
@@ -10,7 +9,6 @@
#include <southbridge/intel/lynxpoint/me.h>
#include <northbridge/intel/haswell/haswell.h>
#include <cpu/intel/haswell/haswell.h>
#include <elog.h>
/* Include EC functions */
#include <ec/google/chromeec/ec.h>
@@ -23,36 +21,11 @@
#define GPIO_WLAN_DISABLE_L 46
#define GPIO_LTE_DISABLE_L 59
static u8 mainboard_smi_ec(void)
{
u8 cmd = google_chromeec_get_event();
u32 pm1_cnt;
/* Log this event */
if (cmd)
elog_gsmi_add_event_byte(ELOG_TYPE_EC_EVENT, cmd);
switch (cmd) {
case EC_HOST_EVENT_LID_CLOSED:
printk(BIOS_DEBUG, "LID CLOSED, SHUTDOWN\n");
/* Go to S5 */
pm1_cnt = inl(get_pmbase() + PM1_CNT);
pm1_cnt |= (0xf << 10);
outl(pm1_cnt, get_pmbase() + PM1_CNT);
break;
}
return cmd;
}
/* gpi_sts is GPIO 47:32 */
void mainboard_smi_gpi(u32 gpi_sts)
{
if (gpi_sts & (1 << (EC_SMI_GPI - 32))) {
/* Process all pending events */
while (mainboard_smi_ec() != 0);
}
if (gpi_sts & (1 << (EC_SMI_GPI - 32)))
chromeec_smi_process_events();
}
void mainboard_smi_sleep(u8 slp_typ)

33
src/mainboard/intel/strago/smihandler.c
View File

@@ -1,14 +1,12 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <acpi/acpi.h>
#include <arch/io.h>
#include <console/console.h>
#include <cpu/x86/smm.h>
#include "ec.h"
#include <ec/google/chromeec/ec.h>
#include <ec/google/chromeec/smm.h>
#include <elog.h>
#include <soc/nvs.h>
#include <soc/pm.h>
@@ -19,41 +17,14 @@
/* The wake gpio is SUS_GPIO[0]. */
#define WAKE_GPIO_EN SUS_GPIO_EN0
static uint8_t mainboard_smi_ec(void)
{
uint8_t cmd = google_chromeec_get_event();
uint16_t pmbase = get_pmbase();
uint32_t pm1_cnt;
/* Log this event */
if (cmd)
elog_gsmi_add_event_byte(ELOG_TYPE_EC_EVENT, cmd);
switch (cmd) {
case EC_HOST_EVENT_LID_CLOSED:
printk(BIOS_DEBUG, "LID CLOSED, SHUTDOWN\n");
/* Go to S5 */
pm1_cnt = inl(pmbase + PM1_CNT);
pm1_cnt |= SLP_EN | (SLP_TYP_S5 << SLP_TYP_SHIFT);
outl(pm1_cnt, pmbase + PM1_CNT);
break;
}
return cmd;
}
/*
* The entire 32-bit ALT_GPIO_SMI register is passed as a parameter. Note, that
* this includes the enable bits in the lower 16 bits.
*/
void mainboard_smi_gpi(uint32_t alt_gpio_smi)
{
if (alt_gpio_smi & (1 << EC_SMI_GPI)) {
/* Process all pending events */
while (mainboard_smi_ec() != 0)
;
}
if (alt_gpio_smi & (1 << EC_SMI_GPI))
chromeec_smi_process_events();
}
void mainboard_smi_sleep(uint8_t slp_typ)

11
src/soc/intel/baytrail/pmutil.c
View File

@@ -12,6 +12,7 @@
#include <device/pci.h>
#include <device/pci_ops.h>
#include <console/console.h>
#include <halt.h>
#include <soc/iomap.h>
#include <soc/lpc.h>
@@ -357,3 +358,13 @@ int platform_is_resuming(void)
return acpi_sleep_from_pm1(inl(ACPI_BASE_ADDRESS + PM1_CNT)) == ACPI_S3;
}
void poweroff(void)
{
uint32_t pm1_cnt;
/* Go to S5 */
pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT);
pm1_cnt |= (0xf << 10);
outl(pm1_cnt, ACPI_BASE_ADDRESS + PM1_CNT);
}

11
src/soc/intel/braswell/pmutil.c
View File

@@ -10,6 +10,7 @@
#include <device/mmio.h>
#include <device/pci.h>
#include <device/pci_ops.h>
#include <halt.h>
#include <console/console.h>
#include <soc/iomap.h>
#include <soc/lpc.h>
@@ -356,3 +357,13 @@ int platform_is_resuming(void)
return acpi_sleep_from_pm1(inl(ACPI_BASE_ADDRESS + PM1_CNT)) == ACPI_S3;
}
void poweroff(void)
{
uint32_t pm1_cnt;
/* Go to S5 */
pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT);
pm1_cnt |= (0xf << 10);
outl(pm1_cnt, ACPI_BASE_ADDRESS + PM1_CNT);
}

11
src/soc/intel/broadwell/pch/pmutil.c
View File

@@ -11,6 +11,7 @@
#include <device/pci_ops.h>
#include <device/device.h>
#include <device/pci.h>
#include <halt.h>
#include <console/console.h>
#include <soc/iomap.h>
#include <soc/lpc.h>
@@ -421,6 +422,16 @@ int platform_is_resuming(void)
return acpi_sleep_from_pm1(inl(get_pmbase() + PM1_CNT)) == ACPI_S3;
}
void poweroff(void)
{
uint32_t pm1_cnt;
/* Go to S5 */
pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT);
pm1_cnt |= (0xf << 10);
outl(pm1_cnt, ACPI_BASE_ADDRESS + PM1_CNT);
}
/* STM Support */
uint16_t get_pmbase(void)
{

11
src/southbridge/intel/common/pmbase.c
View File

@@ -7,6 +7,7 @@
#include <bootmode.h>
#include <device/pci_ops.h>
#include <device/pci_type.h>
#include <halt.h>
#include <stdint.h>
#include "pmbase.h"
@@ -94,6 +95,16 @@ int platform_is_resuming(void)
return acpi_get_sleep_type() == ACPI_S3;
}
void poweroff(void)
{
uint32_t pm1_cnt;
/* Go to S5 */
pm1_cnt = read_pmbase32(PM1_CNT);
pm1_cnt |= (0xf << 10);
write_pmbase32(PM1_CNT, pm1_cnt);
}
#define ACPI_SCI_IRQ 9
void ioapic_get_sci_pin(u8 *gsi, u8 *irq, u8 *flags)