intel/model_2065x: Prepare for dynamic CONFIG_RAMTOP

Change-Id: I616143b55d7c5726dc2475434e3fcb08b8d69bda
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15230
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

src/cpu/intel/model_2065x/Makefile.inc

@@ -20,3 +20,4 @@ smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c
 cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_2065x/microcode.bin
 
 cpu_incs-y += $(src)/cpu/intel/model_2065x/cache_as_ram.inc
+romstage-y += ../car/romstage.c

src/cpu/intel/model_2065x/cache_as_ram.inc

@@ -170,7 +170,12 @@ clear_var_mtrrs:
 before_romstage:
 	post_code(0x29)
 	/* Call romstage.c main function. */
-	call	main
+	call	romstage_main
+
+	/* Save return value from romstage_main. It contains the stack to use
+	 * after cache-as-ram is torn down.
+	 */
+	movl	%eax, %ebx
 
 	post_code(0x2f)
 
@@ -272,7 +277,8 @@ __main:
 	post_code(POST_PREPARE_RAMSTAGE)
 	cld			/* Clear direction flag. */
 
-	movl	$CONFIG_RAMTOP, %esp
+	/* Setup stack as indicated by return value from romstage_main(). */
+	movl	%ebx, %esp
 	movl	%esp, %ebp
 	call	copy_and_run