soc/intel/cannonlake: Add postcar stage support

Initialize postcar frame once finish FSP memoryinit

This patch was merged too early and reverted.
Originally reviewed on https://review.coreboot.org/#/c/20534

Change-Id: Id36aa44bb7a89303bc22e92e0313cf685351690a
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/20688
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/soc/intel/cannonlake/Kconfig

@@ -18,6 +18,8 @@ config CPU_SPECIFIC_OPTIONS
 	select HAVE_MONOTONIC_TIMER
 	select INTEL_CAR_NEM_ENHANCED
 	select PLATFORM_USES_FSP2_0
+	select POSTCAR_CONSOLE
+	select POSTCAR_STAGE
 	select REG_SCRIPT
 	select RELOCATABLE_RAMSTAGE
 	select SOC_INTEL_COMMON
@@ -76,4 +78,13 @@ config CPU_BCLK_MHZ
 	int
 	default 100
 
+# Clock divider parameters for 115200 baud rate
+config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL
+	hex
+	default 0x30
+
+config SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL
+	hex
+	default 0xc35
+
 endif