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soc/intel/cannonlake: Add postcar stage support

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Initialize postcar frame once finish FSP memoryinit

This patch was merged too early and reverted.
Originally reviewed on https://review.coreboot.org/#/c/20534

Change-Id: Id36aa44bb7a89303bc22e92e0313cf685351690a
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/20688
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Lijian Zhao
2017-07-11 12:33:22 -07:00
committed by Aaron Durbin
parent e2ef3cf8e3
commit 8465a81e81
5 changed files with 45 additions and 8 deletions
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10
src/soc/intel/cannonlake/uart.c
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@@ -13,6 +13,8 @@
* GNU General Public License for more details.
*/
#define __SIMPLE_DEVICE__
#include <assert.h>
#include <console/uart.h>
#include <device/pci_def.h>
@@ -25,10 +27,6 @@
#include <soc/pcr_ids.h>
#include <soc/iomap.h>
/* Clock divider parameters for 115200 baud rate */
#define CLK_M_VAL 0x30
#define CLK_N_VAL 0xc35
static const struct port {
struct pad_config pads[2]; /* just TX and RX */
device_t dev;
@@ -56,12 +54,14 @@ void pch_uart_init(void)
p = &uart_ports[CONFIG_UART_FOR_CONSOLE];
base = uart_platform_base(CONFIG_UART_FOR_CONSOLE);
uart_common_init(p->dev, base, CLK_M_VAL, CLK_N_VAL);
uart_common_init(p->dev, base);
gpio_configure_pads(p->pads, ARRAY_SIZE(p->pads));
}
#if IS_ENABLED(CONFIG_DRIVERS_UART_8250MEM)
uintptr_t uart_platform_base(int idx)
{
/* We can only have one serial console at a time */
return UART_DEBUG_BASE_ADDRESS;
}
#endif