From 84937d76fbfb2c7ddf1838d94b166a8ef13660d2 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Wed, 23 Nov 2022 14:48:17 +0100 Subject: [PATCH] soc/intel/alderlake/{chipset.cb,chipset_pch_s.cb}: Set P2SB as hidden MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Set the P2SB device as hidden as FSP-S is hiding the PCI configuration space from coreboot on Alder Lake systems. Signed-off-by: Michał Żygowski Change-Id: I5cfde7c1f6791578a03d73e89bcde31af608f12d --- src/soc/intel/alderlake/chipset.cb | 2 +- src/soc/intel/alderlake/chipset_pch_s.cb | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/alderlake/chipset.cb b/src/soc/intel/alderlake/chipset.cb index 016d3d4862..8a7fa843dc 100644 --- a/src/soc/intel/alderlake/chipset.cb +++ b/src/soc/intel/alderlake/chipset.cb @@ -278,7 +278,7 @@ chip soc/intel/alderlake device pci 1e.2 alias gspi0 off end device pci 1e.3 alias gspi1 off end device pci 1f.0 alias pch_espi on end - device pci 1f.1 alias p2sb off end + device pci 1f.1 alias p2sb hidden end device pci 1f.2 alias pmc hidden end device pci 1f.3 alias hda off end device pci 1f.4 alias smbus off end diff --git a/src/soc/intel/alderlake/chipset_pch_s.cb b/src/soc/intel/alderlake/chipset_pch_s.cb index a2337d6f36..077cdb6649 100644 --- a/src/soc/intel/alderlake/chipset_pch_s.cb +++ b/src/soc/intel/alderlake/chipset_pch_s.cb @@ -242,7 +242,7 @@ chip soc/intel/alderlake device pci 1e.2 alias gspi0 off end device pci 1e.3 alias gspi1 off end device pci 1f.0 alias pch_espi on end - device pci 1f.1 alias p2sb off end + device pci 1f.1 alias p2sb hidden end device pci 1f.2 alias pmc hidden end device pci 1f.3 alias hda off end device pci 1f.4 alias smbus off end