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Update AMD F14 Agesa to support Rev C0 cpus

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This change updates the AMD Agesa code to support the Family 14
rev C0 cpus.  It also fixes (again) a ton of warnings, although
not all of them are gone.  The warning fixes affect code in the
Family 12 tree as well, so there are some small changes therein.
This code has been tested on a Persimmon and passes Abuild.
This is the first (and largest) of a number of commits to complete
the upgrade.

Change-Id: Id28d9bf7931f8baa2a602f6bb096a5a465ccd20d
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Reviewed-on: http://review.coreboot.org/131
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
This commit is contained in:
efdesign98
2011-08-04 12:09:17 -06:00
committed by Patrick Georgi
parent 0df0e14fb5
commit 84cbce2364
277 changed files with 15477 additions and 5393 deletions
Download Patch File Download Diff File Expand all files Collapse all files

7
src/cpu/amd/agesa/family14/Makefile.inc
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@ -63,9 +63,10 @@ agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/PCIe/Family/0x14/F14PcieAlib.c
agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/F14IoCstate.c
agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuIoCstate.c
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/ON/mnprotoon.c
agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/F14MicrocodePatch05000025.c
agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/F14MicrocodePatch0500000B.c
agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/F14MicrocodePatch0500001A.c
agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/F14MicrocodePatch05000028.c
agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/F14MicrocodePatch05000101.c
agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/PCIe/Family/0x14/F14PciePifServices.c
agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/ON/F14OnInitEarlyTable.c
agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuInitEarlyTable.c
@ -103,6 +104,7 @@ agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mmParallelTraining.c
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/LVDDR3/mflvddr3.c
agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/PCIe/Family/0x14/F14PcieComplexConfig.c
agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/cpuF14PowerPlane.c
agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/cpuF14LowPowerInit.c
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/mnreg.c
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/ON/mnflowon.c
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/CHINTLV/mfchi.c
@ -113,6 +115,7 @@ agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Ps/ON/mpuon3.c
agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cahalt.c
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/mt.c
agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/ON/F14OnMicrocodePatchTables.c
agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/ON/F14OnPciTables.c
agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/PCIe/PciePortInit.c
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/mnflow.c
agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuFeatureLeveling.c
@ -138,6 +141,7 @@ agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Gfx/GfxStrapsInit.c
agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Nb/NbInitAtEarly.c
agesa_lib_src += $(AGESA_ROOT)/Lib/amdlib.c
agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuCacheFlushOnHalt.c
agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuCpb.c
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/minit.c
agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/PCIe/Family/0x14/F14PciePhyServices.c
agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/GnbInitAtLate.c
@ -213,6 +217,7 @@ agesa_lib_src += $(AGESA_ROOT)/Proc/Common/AmdInitLate.c
agesa_lib_src += $(AGESA_ROOT)/Proc/HT/htFeat.c
agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Nb/NbInitAtReset.c
agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/ON/F14OnLogicalIdTables.c
agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/ON/F14OnCpb.c
agesa_lib_src += $(AGESA_ROOT)/Legacy/Proc/hobTransfer.c
agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuApicUtilities.c
agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/GnbInitAtEnv.c