sravan/system76-coreboot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Update AMD F14 Agesa to support Rev C0 cpus

Browse Source 
This change updates the AMD Agesa code to support the Family 14
rev C0 cpus.  It also fixes (again) a ton of warnings, although
not all of them are gone.  The warning fixes affect code in the
Family 12 tree as well, so there are some small changes therein.
This code has been tested on a Persimmon and passes Abuild.
This is the first (and largest) of a number of commits to complete
the upgrade.

Change-Id: Id28d9bf7931f8baa2a602f6bb096a5a465ccd20d
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Reviewed-on: http://review.coreboot.org/131
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
This commit is contained in:
efdesign98
2011-08-04 12:09:17 -06:00
committed by Patrick Georgi
parent 0df0e14fb5
commit 84cbce2364
277 changed files with 15477 additions and 5393 deletions
Download Patch File Download Diff File Expand all files Collapse all files

147
src/vendorcode/amd/agesa/f12/Include/ComalInstall.h
View File

@ -1,147 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Install of build options for a Comal platform solution
*
* This file generates the defaults tables for the "Comal" platform solution
* set of processors. The documented build options are imported from a user
* controlled file for processing.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Core
* @e \$Revision: 49803 $ @e \$Date: 2011-03-29 15:20:04 +0800 (Tue, 29 Mar 2011) $
*/
/*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#include "cpuRegisters.h"
#include "cpuFamRegisters.h"
#include "cpuFamilyTranslation.h"
#include "AdvancedApi.h"
#include "heapManager.h"
#include "CreateStruct.h"
#include "cpuFeatures.h"
#include "Table.h"
#include "CommonReturns.h"
#include "cpuEarlyInit.h"
#include "cpuLateInit.h"
#include "GnbInterface.h"
/*****************************************************************************
* Define the RELEASE VERSION string
*
* The Release Version string should identify the next planned release.
* When a branch is made in preparation for a release, the release manager
* should change/confirm that the branch version of this file contains the
* string matching the desired version for the release. The trunk version of
* the file should always contain a trailing 'X'. This will make sure that a
* development build from trunk will not be confused for a released version.
* The release manager will need to remove the trailing 'X' and update the
* version string as appropriate for the release. The trunk copy of this file
* should also be updated/incremented for the next expected version, + trailing 'X'
****************************************************************************/
// This is the delivery package title, "TrinyPI "
// This string MUST be exactly 8 characters long
#define AGESA_PACKAGE_STRING {'T', 'r', 'i', 'n', 'y', 'P', 'I', ' '}
// This is the release version number of the AGESA component
// This string MUST be exactly 12 characters long
#define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '6', '.', '0', 'X', ' ', ' ', ' '}
// The Comal solution is defined to be family 0x15 in the FS1 and FP2 sockets.
#define INSTALL_FS1_SOCKET_SUPPORT TRUE
#define INSTALL_FP2_SOCKET_SUPPORT TRUE
#define INSTALL_FAMILY_15_SUPPORT TRUE
#ifdef BLDOPT_REMOVE_FS1_SOCKET_SUPPORT
#if BLDOPT_REMOVE_FS1_SOCKET_SUPPORT == TRUE
#undef INSTALL_FS1_SOCKET_SUPPORT
#define INSTALL_FS1_SOCKET_SUPPORT FALSE
#endif
#endif
#ifdef BLDOPT_REMOVE_FP2_SOCKET_SUPPORT
#if BLDOPT_REMOVE_FP2_SOCKET_SUPPORT == TRUE
#undef INSTALL_FP2_SOCKET_SUPPORT
#define INSTALL_FP2_SOCKET_SUPPORT FALSE
#endif
#endif
// The following definitions specify the default values for various parameters in which there are
// no clearly defined defaults to be used in the common file. The values below are based on product
// and BKDG content, please consult the AGESA Memory team for consultation.
#define DFLT_SCRUB_DRAM_RATE (0)
#define DFLT_SCRUB_L2_RATE (0)
#define DFLT_SCRUB_L3_RATE (0)
#define DFLT_SCRUB_IC_RATE (0)
#define DFLT_SCRUB_DC_RATE (0)
#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED
#define DFLT_VRM_SLEW_RATE (5000)
#define DFLT_SMBUS0_BASE_ADDRESS 0xB00
#define DFLT_SMBUS1_BASE_ADDRESS 0xB20
#define DFLT_SIO_PME_BASE_ADDRESS 0xE00
#define DFLT_ACPI_PM1_EVT_BLOCK_ADDRESS 0x400
#define DFLT_ACPI_PM1_CNT_BLOCK_ADDRESS 0x404
#define DFLT_ACPI_PM_TMR_BLOCK_ADDRESS 0x408
#define DFLT_ACPI_CPU_CNT_BLOCK_ADDRESS 0x410
#define DFLT_ACPI_GPE0_BLOCK_ADDRESS 0x420
#define DFLT_SPI_BASE_ADDRESS 0xFEC10000
#define DFLT_WATCHDOG_TIMER_BASE_ADDRESS 0xFEC00000
#define DFLT_HPET_BASE_ADDRESS 0xFED00000
#define DFLT_SMI_CMD_PORT 0xB0
#define DFLT_ACPI_PMA_CNT_BLK_ADDRESS 0xFE00
#define DFLT_GEC_BASE_ADDRESS 0xFED61000
#define DFLT_AZALIA_SSID 0x780D1022
#define DFLT_SMBUS_SSID 0x780B1022
#define DFLT_IDE_SSID 0x780C1022
#define DFLT_SATA_AHCI_SSID 0x78011022
#define DFLT_SATA_IDE_SSID 0x78001022
#define DFLT_SATA_RAID5_SSID 0x78031022
#define DFLT_SATA_RAID_SSID 0x78021022
#define DFLT_EHCI_SSID 0x78081022
#define DFLT_OHCI_SSID 0x78071022
#define DFLT_LPC_SSID 0x780E1022
#define DFLT_FCH_GPP_LINK_CONFIG PortA4
#define DFLT_FCH_GPP_PORT0_PRESENT FALSE
#define DFLT_FCH_GPP_PORT1_PRESENT FALSE
#define DFLT_FCH_GPP_PORT2_PRESENT FALSE
#define DFLT_FCH_GPP_PORT3_PRESENT FALSE
#define DFLT_FCH_GPP_PORT0_HOTPLUG FALSE
#define DFLT_FCH_GPP_PORT1_HOTPLUG FALSE
#define DFLT_FCH_GPP_PORT2_HOTPLUG FALSE
#define DFLT_FCH_GPP_PORT3_HOTPLUG FALSE
// Instantiate all solution relevant data.
#include "PlatformInstall.h"

132
src/vendorcode/amd/agesa/f12/Include/DeccanInstall.h
View File

@ -1,132 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Install of build options for a Deccan platform solution
*
* This file generates the defaults tables for the "Deccan" platform solution
* set of processors. The documented build options are imported from a user
* controlled file for processing.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Core
* @e \$Revision: 35276 $ @e \$Date: 2010-07-19 10:47:05 -0700 (Mon, 19 Jul 2010) $
*/
/*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#include "cpuRegisters.h"
#include "cpuFamRegisters.h"
#include "cpuFamilyTranslation.h"
#include "AdvancedApi.h"
#include "heapManager.h"
#include "CreateStruct.h"
#include "cpuFeatures.h"
#include "Table.h"
#include "CommonReturns.h"
#include "cpuEarlyInit.h"
#include "cpuLateInit.h"
#include "GnbInterface.h"
/*****************************************************************************
* Define the RELEASE VERSION string
*
* The Release Version string should identify the next planned release.
* When a branch is made in preparation for a release, the release manager
* should change/confirm that the branch version of this file contains the
* string matching the desired version for the release. The trunk version of
* the file should always contain a trailing 'X'. This will make sure that a
* development build from trunk will not be confused for a released version.
* The release manager will need to remove the trailing 'X' and update the
* version string as appropriate for the release. The trunk copy of this file
* should also be updated/incremented for the next expected version, + trailing 'X'
****************************************************************************/
// This is the delivery package title, "KrishaPI"
// This string MUST be exactly 8 characters long
#define AGESA_PACKAGE_STRING {'K', 'r', 'i', 's', 'h', 'a', 'P', 'I'}
// This is the release version number of the AGESA component
// This string MUST be exactly 12 characters long
#define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '3', '.', '0', 'X', ' ', ' ', ' '}
// The Deccan solution is defined to be family 0x14, models 10h-1fh in the FT2 socket.
#define INSTALL_FT2_SOCKET_SUPPORT TRUE
#define INSTALL_FAMILY_14_SUPPORT TRUE
// The following definitions specify the default values for various parameters in which there are
// no clearly defined defaults to be used in the common file. The values below are based on product
// and BKDG content, please consult the AGESA Memory team for consultation.
#define DFLT_SCRUB_DRAM_RATE (0)
#define DFLT_SCRUB_L2_RATE (0)
#define DFLT_SCRUB_L3_RATE (0)
#define DFLT_SCRUB_IC_RATE (0)
#define DFLT_SCRUB_DC_RATE (0)
#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED
#define DFLT_VRM_SLEW_RATE (5000)
#define DFLT_SMBUS0_BASE_ADDRESS 0xB00
#define DFLT_SMBUS1_BASE_ADDRESS 0xB20
#define DFLT_SIO_PME_BASE_ADDRESS 0xE00
#define DFLT_ACPI_PM1_EVT_BLOCK_ADDRESS 0x400
#define DFLT_ACPI_PM1_CNT_BLOCK_ADDRESS 0x404
#define DFLT_ACPI_PM_TMR_BLOCK_ADDRESS 0x408
#define DFLT_ACPI_CPU_CNT_BLOCK_ADDRESS 0x410
#define DFLT_ACPI_GPE0_BLOCK_ADDRESS 0x420
#define DFLT_SPI_BASE_ADDRESS 0xFEC10000
#define DFLT_WATCHDOG_TIMER_BASE_ADDRESS 0xFEC00000
#define DFLT_HPET_BASE_ADDRESS 0xFED00000
#define DFLT_SMI_CMD_PORT 0xB0
#define DFLT_ACPI_PMA_CNT_BLK_ADDRESS 0xFE00
#define DFLT_GEC_BASE_ADDRESS 0xFED61000
#define DFLT_AZALIA_SSID 0x780D1022
#define DFLT_SMBUS_SSID 0x780B1022
#define DFLT_IDE_SSID 0x780C1022
#define DFLT_SATA_AHCI_SSID 0x78011022
#define DFLT_SATA_IDE_SSID 0x78001022
#define DFLT_SATA_RAID5_SSID 0x78031022
#define DFLT_SATA_RAID_SSID 0x78021022
#define DFLT_EHCI_SSID 0x78081022
#define DFLT_OHCI_SSID 0x78071022
#define DFLT_LPC_SSID 0x780E1022
#define DFLT_FCH_GPP_LINK_CONFIG PortA4
#define DFLT_FCH_GPP_PORT0_PRESENT FALSE
#define DFLT_FCH_GPP_PORT1_PRESENT FALSE
#define DFLT_FCH_GPP_PORT2_PRESENT FALSE
#define DFLT_FCH_GPP_PORT3_PRESENT FALSE
#define DFLT_FCH_GPP_PORT0_HOTPLUG FALSE
#define DFLT_FCH_GPP_PORT1_HOTPLUG FALSE
#define DFLT_FCH_GPP_PORT2_HOTPLUG FALSE
#define DFLT_FCH_GPP_PORT3_HOTPLUG FALSE
// Instantiate all solution relevant data.
#include "PlatformInstall.h"

27
src/vendorcode/amd/agesa/f12/Proc/CPU/Family/cpuFamRegisters.h
View File

@ -80,24 +80,18 @@
// Family 12h equates
#define AMD_FAMILY_12_LN 0x0000000000000020ull
#define AMD_FAMILY_12 (AMD_FAMILY_12_LN)
#define AMD_FAMILY_LN (AMD_FAMILY_12_LN)
#define AMD_FAMILY_12 (AMD_FAMILY_12_LN)
#define AMD_FAMILY_LN (AMD_FAMILY_12_LN)
// Family 14h equates
#define AMD_FAMILY_14_ON 0x0000000000000040ull
#define AMD_FAMILY_ON (AMD_FAMILY_14_ON)
#define AMD_FAMILY_14_KR 0x0000000000000080ull
#define AMD_FAMILY_KR (AMD_FAMILY_14_KR)
#define AMD_FAMILY_14 (AMD_FAMILY_14_ON | AMD_FAMILY_14_KR)
#define AMD_FAMILY_14 (AMD_FAMILY_14_ON)
#define AMD_FAMILY_ON (AMD_FAMILY_14_ON)
// Family 15h equates
#define AMD_FAMILY_15_OR 0x0000000000000100ull
#define AMD_FAMILY_OR (AMD_FAMILY_15_OR)
#define AMD_FAMILY_15_TN 0x0000000000000200ull
#define AMD_FAMILY_TN (AMD_FAMILY_15_TN)
#define AMD_FAMILY_15_KM 0x0000000000000400ull
#define AMD_FAMILY_KM (AMD_FAMILY_15_KM)
#define AMD_FAMILY_15 (AMD_FAMILY_15_OR | AMD_FAMILY_15_TN | AMD_FAMILY_15_KM)
#define AMD_FAMILY_15 (AMD_FAMILY_15_OR)
// Family 16h equates
#define AMD_FAMILY_16 0x0000000000000800ull
@ -203,11 +197,7 @@
#define AMD_F14_ON_Cx (AMD_F14_ON_C0)
#define AMD_F14_ON_ALL (AMD_F14_ON_Ax | AMD_F14_ON_Bx | AMD_F14_ON_Cx)
#define AMD_F14_KR_Ax (AMD_F14_KR_A0 | AMD_F14_KR_A1)
#define AMD_F14_KR_Bx AMD_F14_KR_B0
#define AMD_F14_KR_ALL (AMD_F14_KR_Ax | AMD_F14_KR_Bx)
#define AMD_F14_ALL (AMD_F14_ON_ALL | AMD_F14_KR_ALL | AMD_F14_UNKNOWN)
#define AMD_F14_ALL (AMD_F14_ON_ALL | AMD_F14_UNKNOWN)
// Family 15h CPU_LOGICAL_ID.Revision equates
// -------------------------------------
@ -227,10 +217,7 @@
#define AMD_F15_OR_LT_B1 (AMD_F15_OR_Ax | AMD_F15_OR_B0)
#define AMD_F15_OR_ALL (AMD_F15_OR_Ax | AMD_F15_OR_Bx)
#define AMD_F15_TN_Ax (AMD_F15_TN_A0)
#define AMD_F15_TN_ALL (AMD_F15_TN_Ax)
#define AMD_F15_ALL (AMD_F15_OR_ALL | AMD_F15_TN_ALL | AMD_F15_UNKNOWN)
#define AMD_F15_ALL (AMD_F15_OR_ALL | AMD_F15_UNKNOWN)
// Family 16h CPU_LOGICAL_ID.Revision equates
// TBD

18
src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlib.c
View File

@ -192,7 +192,7 @@ PcieAlibBuildAcpiTable (
LibAmdMemCopy (AlibSsdtBuffer, &AlibSsdt[0], AlibSsdtlength, StdHeader);
// Set PCI MMIO configuration
// AmlObjName = '10DA';
AmlObjName = 0x31304441;
AmlObjName = Int32FromChar ('1', '0', 'D', 'A');
AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName));
ASSERT (AmlObjPtr != NULL);
if (AmlObjPtr != NULL) {
@ -211,7 +211,7 @@ PcieAlibBuildAcpiTable (
ASSERT (PpFuseArray != NULL);
if (PpFuseArray != NULL) {
// AmlObjName = '30DA';
AmlObjName = 0x33304441;
AmlObjName = Int32FromChar ('3', '0', 'D', 'A');
AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName));
ASSERT (AmlObjPtr != NULL);
if (AmlObjPtr != NULL) {
@ -226,7 +226,7 @@ PcieAlibBuildAcpiTable (
Gen1VidIndex = GnbLocateLowestVidIndex (StdHeader);
BootUpVidIndex = GnbLocateHighestVidIndex (StdHeader);
// AmlObjName = '40DA';
AmlObjName = 0x34304441;
AmlObjName = Int32FromChar ('4', '0', 'D', 'A');
AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName));
ASSERT (AmlObjPtr != NULL);
if (AmlObjPtr != NULL) {
@ -235,7 +235,7 @@ PcieAlibBuildAcpiTable (
AgesaStatus = AGESA_FATAL;
}
// AmlObjName = '50DA';
AmlObjName = 0x35304441;
AmlObjName = Int32FromChar ('5', '0', 'D', 'A');
AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName));
ASSERT (AmlObjPtr != NULL);
if (AmlObjPtr != NULL) {
@ -244,7 +244,7 @@ PcieAlibBuildAcpiTable (
AgesaStatus = AGESA_FATAL;
}
// AmlObjName = '01DA';
AmlObjName = 0x30314441;
AmlObjName = Int32FromChar ('0', '1', 'D', 'A');
AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName));
ASSERT (AmlObjPtr != NULL);
if (AmlObjPtr != NULL) {
@ -255,7 +255,7 @@ PcieAlibBuildAcpiTable (
// Set PCIe configuration
if (PcieLocateConfigurationData (StdHeader, &Pcie) == AGESA_SUCCESS) {
// AmlObjName = '20DA';
AmlObjName = 0x32304441;
AmlObjName = Int32FromChar ('2', '0', 'D', 'A');
AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName));
ASSERT (AmlObjPtr != NULL);
if (AmlObjPtr != NULL) {
@ -264,7 +264,7 @@ PcieAlibBuildAcpiTable (
AgesaStatus = AGESA_FATAL;
}
// AmlObjName = '60DA';
AmlObjName = 0x36304441;
AmlObjName = Int32FromChar ('6', '0', 'D', 'A');
AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName));
ASSERT (AmlObjPtr != NULL);
if (AmlObjPtr != NULL) {
@ -278,7 +278,7 @@ PcieAlibBuildAcpiTable (
AgesaStatus = AGESA_FATAL;
}
// AmlObjName = '60DA';
AmlObjName = 0x36304441;
AmlObjName = Int32FromChar ('6', '0', 'D', 'A');
AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName));
ASSERT (AmlObjPtr != NULL);
if (AmlObjPtr != NULL) {
@ -292,7 +292,7 @@ PcieAlibBuildAcpiTable (
AgesaStatus = AGESA_FATAL;
}
// AmlObjName = '70DA';
AmlObjName = 0x37304441;
AmlObjName = Int32FromChar ('7', '0', 'D', 'A');
AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName));
ASSERT (AmlObjPtr != NULL);
if (AmlObjPtr != NULL) {

2
src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/F12PcieAlib.c
View File

@ -110,7 +110,7 @@ PcieFmAlibBuildAcpiTable (
AgesaStatus = AGESA_SUCCESS;
AltVddNbSupport = TRUE;
// AmlObjName = 'A0DA';
AmlObjName = 0x41304441;
AmlObjName = Int32FromChar ('A', '0', 'D', 'A');
AmlObjPtr = GnbLibFind (AlibSsdtPtr, ((ACPI_TABLE_HEADER*) &AlibSsdt[0])->TableLength, (UINT8*) &AmlObjName, sizeof (AmlObjName));
ASSERT (AmlObjPtr != NULL);
if (AmlObjPtr != NULL) {

40
src/vendorcode/amd/agesa/f14/AGESA.h
View File

@ -9,7 +9,7 @@
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Include
* @e \$Revision: 41504 $ @e \$Date: 2010-11-05 21:59:13 +0800 (Fri, 05 Nov 2010) $
* @e \$Revision: 47417 $ @e \$Date: 2011-02-18 12:48:20 -0700 (Fri, 18 Feb 2011) $
*/
/*
*****************************************************************************
@ -822,6 +822,38 @@ typedef enum {
* GNB configuration info
*----------------------------------------------------------------------------
*/
/// LVDS Misc Control Field
typedef struct {
IN UINT8 FpdiMode:1; ///< This item configures LVDS 888bit panel mode
///< @li FALSE = LVDS 888 panel in LDI mode
///< @li TRUE = LVDS 888 panel in FPDI mode
///< @BldCfgItem{BLDCFG_LVDS_MISC_888_FPDI_MODE}
IN UINT8 DlChSwap:1; ///< This item configures LVDS panel lower and upper link mapping
///< @li FALSE = Lower link and upper link not swap
///< @li TRUE = Lower link and upper link are swapped
///< @BldCfgItem{BLDCFG_LVDS_MISC_DL_CH_SWAP}
IN UINT8 VsyncActiveLow:1; ///< This item configures polarity of frame pulse encoded in lvds data stream
///< @li FALSE = Active high Frame Pulse/Vsync
///< @li TRUE = Active low Frame Pulse/Vsync
///< @BldCfgItem{BLDCFG_LVDS_MISC_VSYNC_ACTIVE_LOW}
IN UINT8 HsyncActiveLow:1; ///< This item configures polarity of line pulse encoded in lvds data
///< @li FALSE = Active high Line Pulse
///< @li TRUE = Active low Line Pulse / Hsync
///< @BldCfgItem{BLDCFG_LVDS_MISC_HSYNC_ACTIVE_LOW}
IN UINT8 BLONActiveLow:1; ///< This item configures polarity of signal sent to digital BLON output pin
///< @li FALSE = Not inverted(active high)
///< @li TRUE = Inverted (active low)
///< @BldCfgItem{BLDCFG_LVDS_MISC_BLON_ACTIVE_LOW}
IN UINT8 Reserved:3; ///< Reserved
} LVDS_MISC_CONTROL_FIELD;
/// LVDS Misc Control
typedef union _LVDS_MISC_CONTROL {
IN LVDS_MISC_CONTROL_FIELD Field; ///< LVDS_MISC_CONTROL_FIELD
IN UINT8 Value; ///< LVDS Misc Control Value
} LVDS_MISC_CONTROL;
/// Configuration settings for GNB.
typedef struct {
IN UINT8 Gnb3dStereoPinIndex; ///< 3D Stereo Pin ID.
@ -837,6 +869,9 @@ typedef struct {
///< BldCfgItem{BLDCFG_GFX_LVDS_SPREAD_SPECTRUM}
IN UINT16 LvdsSpreadSpectrumRate; ///< Spread spectrum frequency used by SS hardware logic in unit of 10Hz, 0 - default frequency 40kHz
///< BldCfgItem{BLDCFG_GFX_LVDS_SPREAD_SPECTRUM_RATE}
IN LVDS_MISC_CONTROL LvdsMiscControl;///< This item configures LVDS swap/Hsync/Vsync/BLON
IN UINT16 PcieRefClkSpreadSpectrum; ///< Spread spectrum value in 0.01 %
///< @BldCfgItem{BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM}
} GNB_ENV_CONFIGURATION;
/// GNB configuration info
@ -2240,6 +2275,9 @@ typedef struct {
///< Build-time customizable only - @BldCfgItem{BLDCFG_GFX_LVDS_SPREAD_SPECTRUM}
IN UINT16 CfgLvdsSpreadSpectrumRate; ///< Lvds Spread Spectrum Rate
///< Build-time customizable only - @BldCfgItem{BLDCFG_GFX_LVDS_SPREAD_SPECTRUM_RATE}
IN LVDS_MISC_CONTROL CfgLvdsMiscControl; ///< The LVDS Misc control
IN UINT16 CfgPcieRefClkSpreadSpectrum; ///< PCIe Reference Clock Spread Spectrum
///< Build-time customizable only - @BldCfgItem{BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM}
IN BOOLEAN Reserved; ///< reserved...
} BUILD_OPT_CFG;

2
src/vendorcode/amd/agesa/f14/AMD.h
View File

@ -167,7 +167,7 @@ typedef struct {
IN UINT32 AltImageBasePtr; ///< Alternate Image location
IN CALLOUT_ENTRY CalloutPtr; ///< For Callout from AGESA
IN UINT8 HeapStatus; ///< For heap status from boot time slide.
IN UINT64 HeapBasePtr; ///< Location of the heap
IN VOID *HeapBasePtr; ///< Location of the heap
IN OUT UINT8 Reserved[7]; ///< This space is reserved for future use.
} AMD_CONFIG_PARAMS;

18
src/vendorcode/amd/agesa/f14/Include/AdvancedApi.h
View File

@ -10,14 +10,13 @@
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Include
* @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
* @e \$Revision: 44325 $ @e \$Date: 2010-12-22 03:29:53 -0700 (Wed, 22 Dec 2010) $
*/
/*
*****************************************************************************
/*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
@ -28,7 +27,7 @@
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@ -39,7 +38,7 @@
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*
* ***************************************************************************
*
*/
@ -165,4 +164,11 @@ BOOLEAN
memDefFalse (
VOID
);
VOID
MemRecDefRet (VOID);
BOOLEAN
MemRecDefTrue (VOID);
#endif // _ADVANCED_API_H_

9
src/vendorcode/amd/agesa/f14/Include/BrazosInstall.h
View File

@ -11,10 +11,9 @@
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Core
* @e \$Revision: 40817 $ @e \$Date: 2010-10-28 03:28:12 +0800 (Thu, 28 Oct 2010) $
* @e \$Revision: 53801 $ @e \$Date: 2011-05-25 12:03:55 -0600 (Wed, 25 May 2011) $
*/
/*
*****************************************************************************
/*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
@ -41,7 +40,7 @@
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ***************************************************************************
****************************************************************************
*
*/
@ -77,7 +76,7 @@
// This is the release version number of the AGESA component
// This string MUST be exactly 12 characters long
#define AGESA_VERSION_STRING {'V', '1', '.', '0', '.', '0', '.', '1', ' ', ' ', ' ', ' '}
#define AGESA_VERSION_STRING {'V', '1', '.', '1', '.', '0', '.', '0', ' ', ' ', ' ', ' '}
// The Brazos solution is defined to be family 0x14 in the FT1 socket.

7
src/vendorcode/amd/agesa/f14/Include/Filecode.h
View File

@ -12,7 +12,7 @@
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Include
* @e \$Revision: 40742 $ @e \$Date: 2010-10-27 04:04:08 +0800 (Wed, 27 Oct 2010) $
* @e \$Revision: 46485 $ @e \$Date: 2011-02-03 09:03:14 -0700 (Thu, 03 Feb 2011) $
*/
/*
*****************************************************************************
@ -426,12 +426,15 @@
#define PROC_CPU_FAMILY_0X14_CPUF14PSTATE_FILECODE (0xCA0D)
#define PROC_CPU_FAMILY_0X14_F14C6STATE_FILECODE (0xCA0E)
#define PROC_CPU_FAMILY_0X14_F14IOCSTATE_FILECODE (0xCA0F)
#define PROC_CPU_FAMILY_0X14_CPUF14PERCOREPCITABLES_FILECODE (0xCA10)
#define PROC_CPU_FAMILY_0X14_CPUF14LOWPOWERINIT_FILECODE (0xCA11)
#define PROC_CPU_FAMILY_0X14_ON_F14ONLOGICALIDTABLES_FILECODE (0xCA21)
#define PROC_CPU_FAMILY_0X14_ON_F14ONMICROCODEPATCHTABLES_FILECODE (0xCA22)
#define PROC_CPU_FAMILY_0X14_ON_F14ONEQUIVALENCETABLE_FILECODE (0xCA23)
#define PROC_CPU_FAMILY_0X14_ON_F14ONINITEARLYTABLE_FILECODE (0xCA24)
#define PROC_CPU_FAMILY_0X14_CPUF14PERCOREPCITABLES_FILECODE (0xCA25)
#define PROC_CPU_FAMILY_0X14_ON_F14ONEARLYSAMPLES_FILECODE (0xCA26)
#define PROC_CPU_FAMILY_0X14_ON_F14ONCPB_FILECODE (0xCA2C)
#define PROC_CPU_FAMILY_0X14_ON_F14ONPCITABLES_FILECODE (0xCA2D)
// Family 15h
#define PROC_CPU_FAMILY_0X15_CPUCOMMONF15UTILITIES_FILECODE (0xCB01)

10
src/vendorcode/amd/agesa/f14/Include/GnbInterface.h
View File

@ -9,7 +9,7 @@
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: GNB
* @e \$Revision: 37658 $ @e \$Date: 2010-09-09 15:25:38 +0800 (Thu, 09 Sep 2010) $
* @e \$Revision: 44325 $ @e \$Date: 2010-12-22 03:29:53 -0700 (Wed, 22 Dec 2010) $
*
*/
/*
@ -17,7 +17,7 @@
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
@ -28,7 +28,7 @@
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@ -39,8 +39,8 @@
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ***************************************************************************
*
****************************************************************************
*
*/

62
src/vendorcode/amd/agesa/f14/Include/GnbInterfaceStub.h
View File

@ -9,40 +9,40 @@
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: GNB
* @e \$Revision: 37658 $ @e \$Date: 2010-09-09 15:25:38 +0800 (Thu, 09 Sep 2010) $
* @e \$Revision: 44325 $ @e \$Date: 2010-12-22 03:29:53 -0700 (Wed, 22 Dec 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ***************************************************************************
*
*/
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ***************************************************************************
*
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D

20
src/vendorcode/amd/agesa/f14/Include/Ids.h
View File

@ -9,14 +9,14 @@
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: IDS
* @e \$Revision: 38634 $ @e \$Date: 2010-09-27 21:39:01 +0800 (Mon, 27 Sep 2010) $
* @e \$Revision: 44325 $ @e \$Date: 2010-12-22 03:29:53 -0700 (Wed, 22 Dec 2010) $
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
@ -27,7 +27,7 @@
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@ -38,7 +38,7 @@
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*
* ***************************************************************************
*
*/
@ -568,12 +568,12 @@ typedef enum { //vv- for debug reference only
#define IDS_HDT_CONSOLE(f, s, ...)
#endif
#else
#pragma warning(disable: 4127)
#ifdef __GNUC__
#ifndef __GNUC__
#pragma warning(disable: 4127)
#define IDS_HDT_CONSOLE(f, s, ...)
#else
#define IDS_HDT_CONSOLE(f, s, ...)
#endif
#else
#define IDS_HDT_CONSOLE(f, s, ...) printk (BIOS_DEBUG, s, ##__VA_ARGS__);
#endif
#endif
#define IDS_HDT_CONSOLE_FLUSH_BUFFER(x)
@ -625,7 +625,7 @@ typedef enum { //vv- for debug reference only
#endif
///For IDS feat use
#define IDS_FAMILY_ALL 0x0ull
#define IDS_FAMILY_ALL 0xFFFFFFFFFFFFFFFFull
#define IDS_BSP_ONLY TRUE
#define IDS_ALL_CORES FALSE

18
src/vendorcode/amd/agesa/f14/Include/OptionCpbInstall.h
View File

@ -56,10 +56,11 @@
#define OPTION_CPB_FEAT
#define F10_CPB_SUPPORT
#define F12_CPB_SUPPORT
#define F14_ON_CPB_SUPPORT
#define F15_CPB_SUPPORT
#if OPTION_CPB == TRUE
#if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_LATE == TRUE)
#if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_LATE == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE)
// Family 10h
#ifdef OPTION_FAMILY10H
#if OPTION_FAMILY10H == TRUE
@ -88,6 +89,20 @@
#endif
#endif
// Family 14h
#ifdef OPTION_FAMILY14H
#if OPTION_FAMILY14H == TRUE
#if OPTION_FAMILY14H_ON == TRUE
extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCpb;
#undef OPTION_CPB_FEAT
#define OPTION_CPB_FEAT &CpuFeatureCpb,
extern CONST CPB_FAMILY_SERVICES ROMDATA F14OnCpbSupport;
#undef F14_ON_CPB_SUPPORT
#define F14_ON_CPB_SUPPORT {AMD_FAMILY_14_ON, &F14OnCpbSupport},
#endif
#endif
#endif
// Family 15h
#ifdef OPTION_FAMILY15H
#if OPTION_FAMILY15H == TRUE
@ -109,6 +124,7 @@ CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA CpbFamilyServiceArray[] =
{
F10_CPB_SUPPORT
F12_CPB_SUPPORT
F14_ON_CPB_SUPPORT
F15_CPB_SUPPORT
{0, NULL}
};

22
src/vendorcode/amd/agesa/f14/Include/OptionFamily14hInstall.h
View File

@ -69,7 +69,7 @@ extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF14BrandIdString2;
extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF14CacheInfo;
extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF14SysPmTable;
extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF14WheaInitData;
extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetEmptyArray;
//extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetEmptyArray;
extern F_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO F14GetPlatformTypeSpecificInfo;
extern F_CPU_GET_IDD_MAX F14GetProcIddMax;
extern CONST REGISTER_TABLE ROMDATA F14PciRegisterTable;
@ -90,6 +90,7 @@ extern F_IS_NB_PSTATE_ENABLED F14IsNbPstateEnabled;
#if OPTION_FAMILY14H_ON == TRUE
extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF14OnMicroCodePatchesStruct;
extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF14OnMicrocodeEquivalenceTable;
extern CONST REGISTER_TABLE ROMDATA F14OnPciRegisterTable;
#if USES_REGISTER_TABLES == TRUE
CONST REGISTER_TABLE ROMDATA *F14OnRegisterTables[] =
@ -106,6 +107,9 @@ extern F_IS_NB_PSTATE_ENABLED F14IsNbPstateEnabled;
&F14EarlySampleMsrRegisterTable,
#endif
#endif
#if MODEL_SPECIFIC_PCI == TRUE
&F14OnPciRegisterTable,
#endif
// the end.
NULL
};
@ -325,7 +329,8 @@ extern F_IS_NB_PSTATE_ENABLED F14IsNbPstateEnabled;
#if GET_PATCHES == TRUE
#define F14_ON_UCODE_0B
#define F14_ON_UCODE_1A
#define F14_ON_UCODE_25
#define F14_ON_UCODE_28
#define F14_ON_UCODE_101
// If a patch is required for recovery mode to function properly, add a
// conditional for AGESA_ENTRY_INIT_RECOVERY, and pull it in.
@ -339,16 +344,21 @@ extern F_IS_NB_PSTATE_ENABLED F14IsNbPstateEnabled;
#undef F14_ON_UCODE_1A
#define F14_ON_UCODE_1A &CpuF14MicrocodePatch0500001A,
#endif
extern CONST MICROCODE_PATCHES ROMDATA CpuF14MicrocodePatch05000025;
#undef F14_ON_UCODE_25
#define F14_ON_UCODE_25 &CpuF14MicrocodePatch05000025,
extern CONST MICROCODE_PATCHES ROMDATA CpuF14MicrocodePatch05000028;
#undef F14_ON_UCODE_28
#define F14_ON_UCODE_28 &CpuF14MicrocodePatch05000028,
extern CONST MICROCODE_PATCHES ROMDATA CpuF14MicrocodePatch05000101;
#undef F14_ON_UCODE_101
#define F14_ON_UCODE_101 &CpuF14MicrocodePatch05000101,
#endif
CONST MICROCODE_PATCHES ROMDATA *CpuF14OnMicroCodePatchArray[] =
{
F14_ON_UCODE_101
F14_ON_UCODE_28
F14_ON_UCODE_0B
F14_ON_UCODE_1A
F14_ON_UCODE_25
NULL
};

7
src/vendorcode/amd/agesa/f14/Include/OptionGnb.h
View File

@ -81,7 +81,12 @@ typedef struct {
BOOLEAN LclkDpmEn; ///< Default for LCLK DPM
BOOLEAN GmcPowerGateStutterOnly; ///< Force GMC power gate to stutter only
BOOLEAN SmuSclkClockGatingEnable;///< Control SMU SCLK gating
BOOLEAN PcieAspmBlackListEnable; ///< Control Pcie Aspm Black List
BOOLEAN PcieAspmBlackListEnable; ///< Control Pcie Aspm Black List
UINT32 LinkReceiverDetectionPooling; ///< Receiver pooling detection time in us.
UINT32 LinkL0Pooling; ///< Pooling for link to get to L0 in us
UINT32 LinkGpioResetAssertionTime; ///< Gpio reset assertion time in us
UINT32 LinkResetToTrainingTime; ///< Time duration between deassert GPIO reset and release training in us ///
UINT8 TrainingAlgorithm; ///< Training algorithm (see PCIE_TRAINING_ALGORITHM)
} GNB_BUILD_OPTIONS;
/*----------------------------------------------------------------------------------------

45
src/vendorcode/amd/agesa/f14/Include/OptionGnbInstall.h
View File

@ -10,7 +10,7 @@
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Options
* @e \$Revision: 40151 $ @e \$Date: 2010-10-20 06:38:17 +0800 (Wed, 20 Oct 2010) $
* @e \$Revision: 44325 $ @e \$Date: 2010-12-22 03:29:53 -0700 (Wed, 22 Dec 2010) $
*/
/*
*****************************************************************************
@ -58,6 +58,9 @@
#define GNB_TYPE_KR FALSE
#define GNB_TYPE_TN FALSE
#include "Gnb.h"
#include "GnbPcie.h"
#ifndef CFG_IGFX_AS_PCIE_EP
#define CFG_IGFX_AS_PCIE_EP TRUE
#endif
@ -94,13 +97,40 @@
#define CFG_PCIE_ASPM_BLACK_LIST_ENABLE TRUE
#endif
#ifndef CFG_GNB_PCIE_LINK_RECEIVER_DETECTION_POOLING
#define CFG_GNB_PCIE_LINK_RECEIVER_DETECTION_POOLING (60 * 1000)
#endif
#ifndef CFG_GNB_PCIE_LINK_L0_POOLING
#define CFG_GNB_PCIE_LINK_L0_POOLING (60 * 1000)
#endif
#ifndef CFG_GNB_PCIE_LINK_GPIO_RESET_ASSERT_TIME
#define CFG_GNB_PCIE_LINK_GPIO_RESET_ASSERT_TIME (2 * 1000)
#endif
#ifndef CFG_GNB_PCIE_LINK_RESET_TO_TRAINING_TIME
#define CFG_GNB_PCIE_LINK_RESET_TO_TRAINING_TIME (2 * 1000)
#endif
#ifdef BLDCFG_PCIE_TRAINING_ALGORITHM
#define CFG_GNB_PCIE_TRAINING_ALGORITHM BLDCFG_PCIE_TRAINING_ALGORITHM
#else
#define CFG_GNB_PCIE_TRAINING_ALGORITHM PcieTrainingStandard
#endif
GNB_BUILD_OPTIONS GnbBuildOptions = {
CFG_IGFX_AS_PCIE_EP,
CFG_LCLK_DEEP_SLEEP_EN,
CFG_LCLK_DPM_EN,
CFG_GMC_POWER_GATE_STUTTER_ONLY,
CFG_SMU_SCLK_CLOCK_GATING_ENABLE,
CFG_PCIE_ASPM_BLACK_LIST_ENABLE
CFG_PCIE_ASPM_BLACK_LIST_ENABLE,
CFG_GNB_PCIE_LINK_RECEIVER_DETECTION_POOLING,
CFG_GNB_PCIE_LINK_L0_POOLING,
CFG_GNB_PCIE_LINK_GPIO_RESET_ASSERT_TIME,
CFG_GNB_PCIE_LINK_RESET_TO_TRAINING_TIME,
CFG_GNB_PCIE_TRAINING_ALGORITHM
};
@ -203,6 +233,16 @@ GNB_BUILD_OPTIONS GnbBuildOptions = {
#else
#define OPTION_NBINITATPOST_ENTRY
#endif
//---------------------------------------------------------------------------------------------------
#ifndef OPTION_PCIE_POST_EALRY_INIT
#define OPTION_PCIE_POST_EALRY_INIT TRUE
#endif
#if (OPTION_PCIE_POST_EALRY_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE)
OPTION_GNB_FEATURE PcieInitAtPostEarly;
#define OPTION_PCIEINITATPOSTEARLY_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, PcieInitAtPostEarly},
#else
#define OPTION_PCIEINITATPOSTEARLY_ENTRY
#endif
//---------------------------------------------------------------------------------------------------
#ifndef OPTION_PCIE_POST_INIT
#define OPTION_PCIE_POST_INIT TRUE
@ -215,6 +255,7 @@ GNB_BUILD_OPTIONS GnbBuildOptions = {
#endif
//---------------------------------------------------------------------------------------------------
OPTION_GNB_CONFIGURATION GnbPostFeatureTable[] = {
OPTION_PCIEINITATPOSTEARLY_ENTRY
OPTION_GFXCONFIGPOSTINTERFACE_ENTRY
OPTION_GFXINITATPOST_ENTRY
{0, NULL}

12
src/vendorcode/amd/agesa/f14/Include/OptionMemory.h
View File

@ -320,10 +320,22 @@ BOOLEAN MemFDefRet (
BOOLEAN MemMDefRet (
IN MEM_MAIN_DATA_BLOCK *MMPtr
);
BOOLEAN MemMDefRetFalse (
IN MEM_MAIN_DATA_BLOCK *MMPtr
);
/* Table Feature Default Return */
UINT8 MemFTableDefRet (
IN OUT MEM_TABLE_ALIAS **MTPtr
);
BOOLEAN MemNIdentifyDimmConstructorRetDef (
IN OUT MEM_NB_BLOCK *NBPtr,
IN OUT MEM_DATA_STRUCT *MemPtr,
IN UINT8 NodeID
);
/* S3 Feature Default Return */
BOOLEAN MemFS3DefConstructorRet (
IN OUT VOID *S3NBPtr,

33
src/vendorcode/amd/agesa/f14/Include/OptionMemoryInstall.h
View File

@ -314,74 +314,65 @@ BOOLEAN MemFS3DefConstructorRet (
* based upon the number of processor families that the BIOS will support.
*/
extern MEM_FLOW_CFG MemMFlowDef;
#if (OPTION_MEMCTLR_DR == TRUE)
extern MEM_FLOW_CFG MemMFlowDr;
#define MEM_MAIN_FLOW_CONTROL_PTR_Dr MemMFlowDr,
#else
extern MEM_FLOW_CFG MemMFlowDef;
#define MEM_MAIN_FLOW_CONTROL_PTR_Dr MemMFlowDef,
#endif
#if (OPTION_MEMCTLR_DA == TRUE)
extern MEM_FLOW_CFG MemMFlowDA;
#define MEM_MAIN_FLOW_CONTROL_PTR_DA MemMFlowDA,
#else
extern MEM_FLOW_CFG MemMFlowDef;
#define MEM_MAIN_FLOW_CONTROL_PTR_DA MemMFlowDef,
#endif
#if (OPTION_MEMCTLR_HY == TRUE)
extern MEM_FLOW_CFG MemMFlowHy;
#define MEM_MAIN_FLOW_CONTROL_PTR_Hy MemMFlowHy,
#else
extern MEM_FLOW_CFG MemMFlowDef;
#define MEM_MAIN_FLOW_CONTROL_PTR_Hy MemMFlowDef,
#endif
#if (OPTION_MEMCTLR_OR == TRUE)
extern MEM_FLOW_CFG MemMFlowOr;
#define MEM_MAIN_FLOW_CONTROL_PTR_OR MemMFlowOr,
#else
extern MEM_FLOW_CFG MemMFlowDef;
#define MEM_MAIN_FLOW_CONTROL_PTR_OR MemMFlowDef,
#endif
#if (OPTION_MEMCTLR_LN == TRUE)
extern MEM_FLOW_CFG MemMFlowLN;
#define MEM_MAIN_FLOW_CONTROL_PTR_LN MemMFlowLN,
#else
extern MEM_FLOW_CFG MemMFlowDef;
#define MEM_MAIN_FLOW_CONTROL_PTR_LN MemMFlowDef,
#endif
#if (OPTION_MEMCTLR_C32 == TRUE)
extern MEM_FLOW_CFG MemMFlowC32;
#define MEM_MAIN_FLOW_CONTROL_PTR_C32 MemMFlowC32,
#else
extern MEM_FLOW_CFG MemMFlowDef;
#define MEM_MAIN_FLOW_CONTROL_PTR_C32 MemMFlowDef,
#endif
#if (OPTION_MEMCTLR_ON == TRUE)
extern MEM_FLOW_CFG MemMFlowON;
#define MEM_MAIN_FLOW_CONTROL_PTR_ON MemMFlowON,
#else
extern MEM_FLOW_CFG MemMFlowDef;
#define MEM_MAIN_FLOW_CONTROL_PTR_ON MemMFlowDef,
#endif
#if (OPTION_MEMCTLR_Ni == TRUE)
extern MEM_FLOW_CFG MemMFlowDA;
#define MEM_MAIN_FLOW_CONTROL_PTR_Ni MemMFlowDA,
#else
extern MEM_FLOW_CFG MemMFlowDef;
#define MEM_MAIN_FLOW_CONTROL_PTR_Ni MemMFlowDef,
#endif
#if (OPTION_MEMCTLR_RB == TRUE)
extern MEM_FLOW_CFG MemMFlowRb;
#define MEM_MAIN_FLOW_CONTROL_PTR_RB MemMFlowRb,
#else
extern MEM_FLOW_CFG MemMFlowDef;
#define MEM_MAIN_FLOW_CONTROL_PTR_RB MemMFlowDef,
#endif
#if (OPTION_MEMCTLR_PH == TRUE)
extern MEM_FLOW_CFG MemMFlowPh;
#define MEM_MAIN_FLOW_CONTROL_PTR_PH MemMFlowPh,
#else
extern MEM_FLOW_CFG MemMFlowDef;
#define MEM_MAIN_FLOW_CONTROL_PTR_PH MemMFlowDef,
#endif
@ -464,13 +455,6 @@ BOOLEAN MemFS3DefConstructorRet (
#define MEM_FEATURE_ECCX8 MemMDefRet
#endif
#if (OPTION_EMP == TRUE)
extern OPTION_MEM_FEATURE_NB MemFInitEMP;
#define MEM_FEATURE_EMP MemFInitEMP
#else
#define MEM_FEATURE_EMP MemFDefRet
#endif
extern OPTION_MEM_FEATURE_MAIN MemMMctMemClr;
#define MEM_MAIN_FEATURE_MEM_CLEAR MemMMctMemClr
@ -505,11 +489,11 @@ BOOLEAN MemFS3DefConstructorRet (
extern OPTION_MEM_FEATURE_MAIN MemMUmaAlloc;
#define MEM_MAIN_FEATURE_UMAALLOC MemMUmaAlloc
extern OPTION_MEM_FEATURE_MAIN MemMStandardTraining;
#if (OPTION_PARALLEL_TRAINING == TRUE)
extern OPTION_MEM_FEATURE_MAIN MemMParallelTraining;
#define MEM_MAIN_FEATURE_TRAINING MemMParallelTraining
#else
extern OPTION_MEM_FEATURE_MAIN MemMStandardTraining;
#define MEM_MAIN_FEATURE_TRAINING MemMStandardTraining
#endif
@ -555,7 +539,7 @@ BOOLEAN MemFS3DefConstructorRet (
#define MEM_TECH_FEATURE_HW_DRAMINIT MemTFeatDef
#endif
#if (OPTION_SW_DRAM_INIT == TRUE)
extern MEM_TECH_FEAT MemTDramInitSw3;
// extern MEM_TECH_FEAT MemTDramInitSw3;
#define MEM_TECH_FEATURE_SW_DRAMINIT MemTDramInitSw3
#else
#define MEM_TECH_FEATURE_SW_DRAMINIT MemTFeatDef
@ -956,7 +940,6 @@ BOOLEAN MemFS3DefConstructorRet (
#undef MEM_MAIN_FEATURE_TRAINING
#undef MEM_FEATURE_TRAINING
extern OPTION_MEM_FEATURE_MAIN MemMStandardTraining;
#define MEM_MAIN_FEATURE_TRAINING MemMStandardTraining
extern OPTION_MEM_FEATURE_NB MemFStandardTraining;
#define MEM_FEATURE_TRAINING MemFStandardTraining
@ -2284,9 +2267,9 @@ BOOLEAN MemFS3DefConstructorRet (
TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3,
TECH_TRAIN_MAX_RD_LAT_DDR3
};
extern OPTION_MEM_FEATURE_NB MemNDQSTiming3Nb;
// extern OPTION_MEM_FEATURE_NB MemNDQSTiming3Nb;
#define NB_TRAIN_FLOW_DDR3 MemNDQSTiming3Nb
extern OPTION_MEM_FEATURE_NB memNSequenceDDR3Nb;
// extern OPTION_MEM_FEATURE_NB memNSequenceDDR3Nb;
#define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_ON {MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION,memNSequenceDDR3Nb, memNEnableTrainSequenceON, &memTechTrainingFeatSequenceDDR3ON },
#else
#undef TECH_TRAIN_ENTER_HW_TRN_DDR3
@ -3253,9 +3236,9 @@ BOOLEAN MemFS3DefConstructorRet (
NULL
};
CONST UINTN SIZE_OF_PLATFORM = (sizeof (memPlatformTypeInstalled) / sizeof (MEM_PLATFORM_CFG*));
#if SIZE_OF_PLATFORM > MAX_PLATFORM_TYPES
#error Size of memPlatformTypeInstalled array larger than MAX_PLATFORM_TYPES
#endif
// #if SIZE_OF_PLATFORM > MAX_PLATFORM_TYPES
// #error Size of memPlatformTypeInstalled array larger than MAX_PLATFORM_TYPES
// #endif
/*---------------------------------------------------------------------------------------------------
* EXTRACTABLE PLATFORM SPECIFIC CONFIGURATION

2
src/vendorcode/amd/agesa/f14/Include/OptionMemoryRecoveryInstall.h
View File

@ -579,7 +579,7 @@
*
*---------------------------------------------------------------------------------------------------
*/
MEM_NB_SUPPORT MemRecNBInstalled[] = {
MEM_NB_SUPPORT* MemRecNBInstalled[] = {
NULL
};
/*----------------------------------------------------------------------

2
src/vendorcode/amd/agesa/f14/Include/OptionPstateInstall.h
View File

@ -101,7 +101,7 @@
#error BLDOPT: Option not defined: "OPTION_ACPI_PSTATES"
#endif
#if (OPTION_ACPI_PSTATES == TRUE)
OPTION_SSDT_FEATURE GenerateSsdt;
// OPTION_SSDT_FEATURE GenerateSsdt;
#define USER_SSDT_MAIN GenerateSsdt
#ifndef OPTION_MULTISOCKET
#error BLDOPT: Option not defined: "OPTION_MULTISOCKET"

57
src/vendorcode/amd/agesa/f14/Include/PlatformInstall.h
View File

@ -11,7 +11,7 @@
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Core
* @e \$Revision: 41504 $ @e \$Date: 2010-11-05 21:59:13 +0800 (Fri, 05 Nov 2010) $
* @e \$Revision: 47417 $ @e \$Date: 2011-02-18 12:48:20 -0700 (Fri, 18 Feb 2011) $
*/
/*
*****************************************************************************
@ -79,7 +79,7 @@
VOLATILE AMD_MODULE_HEADER mCpuModuleID = {
//ModuleHeaderSignature
// Remove 'DOM$' as temp solution before update BinUtil.exe ,
'0000',
Int32FromChar ('0', '0', '0', '0'),
//ModuleIdentifier[8]
AGESA_ID,
//ModuleVersion[12]
@ -1015,6 +1015,8 @@ VOLATILE AMD_MODULE_HEADER mCpuModuleID = {
#define OPTION_GFX_RECOVERY TRUE
#undef OPTION_C6_STATE
#define OPTION_C6_STATE TRUE
#undef OPTION_CPB
#define OPTION_CPB TRUE
#undef OPTION_IO_CSTATE
#define OPTION_IO_CSTATE TRUE
#undef OPTION_S3SCRIPT
@ -1937,6 +1939,12 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE;
#define CFG_GFX_LVDS_SPREAD_SPECTRUM_RATE 0
#endif
#ifdef BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM
#define CFG_PCIE_REFCLK_SPREAD_SPECTRUM BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM
#else
#define CFG_PCIE_REFCLK_SPREAD_SPECTRUM 0
#endif
#ifdef BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS
#define CFG_TEMP_PCIE_MMIO_BASE_ADDRESS BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS
#else
@ -1963,6 +1971,35 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE;
#endif
#endif
#ifdef BLDCFG_LVDS_MISC_888_FPDI_MODE
#define CFG_LVDS_MISC_888_FPDI_MODE BLDCFG_LVDS_MISC_888_FPDI_MODE
#else
#define CFG_LVDS_MISC_888_FPDI_MODE FALSE
#endif
#ifdef BLDCFG_LVDS_MISC_DL_CH_SWAP
#define CFG_LVDS_MISC_DL_CH_SWAP BLDCFG_LVDS_MISC_DL_CH_SWAP
#else
#define CFG_LVDS_MISC_DL_CH_SWAP FALSE
#endif
#ifdef BLDCFG_LVDS_MISC_VSYNC_ACTIVE_LOW
#define CFG_LVDS_MISC_VSYNC_ACTIVE_LOW BLDCFG_LVDS_MISC_VSYNC_ACTIVE_LOW
#else
#define CFG_LVDS_MISC_VSYNC_ACTIVE_LOW FALSE
#endif
#ifdef BLDCFG_LVDS_MISC_HSYNC_ACTIVE_LOW
#define CFG_LVDS_MISC_HSYNC_ACTIVE_LOW BLDCFG_LVDS_MISC_HSYNC_ACTIVE_LOW
#else
#define CFG_LVDS_MISC_HSYNC_ACTIVE_LOW FALSE
#endif
#ifdef BLDCFG_LVDS_MISC_BLON_ACTIVE_LOW
#define CFG_LVDS_MISC_BLON_ACTIVE_LOW BLDCFG_LVDS_MISC_BLON_ACTIVE_LOW
#else
#define CFG_LVDS_MISC_BLON_ACTIVE_LOW FALSE
#endif
/*---------------------------------------------------------------------------
* Processing the options: Third, perform the option cross checks
*--------------------------------------------------------------------------*/
@ -2281,6 +2318,14 @@ BUILD_OPT_CFG UserOptions = {
CFG_GFX_LVDS_SPREAD_SPECTRUM, // CfgLvdsSpreadSpectrum
CFG_GFX_LVDS_SPREAD_SPECTRUM_RATE, // CfgLvdsSpreadSpectrumRate
{{
CFG_LVDS_MISC_888_FPDI_MODE, // CfgLvdsMiscControl
CFG_LVDS_MISC_DL_CH_SWAP, // CfgLvdsMiscControl
CFG_LVDS_MISC_VSYNC_ACTIVE_LOW, // CfgLvdsMiscControl
CFG_LVDS_MISC_HSYNC_ACTIVE_LOW, // CfgLvdsMiscControl
CFG_LVDS_MISC_BLON_ACTIVE_LOW, // CfgLvdsMiscControl
}},
CFG_PCIE_REFCLK_SPREAD_SPECTRUM, // CfgPcieRefClkSpreadSpectrum
0, //reserved...
};
@ -2384,7 +2429,7 @@ CONST FUNCTION_PARAMS_INFO ROMDATA FuncParamsInfo[] =
AMD_LATE_RUN_AP_TASK_HANDLE
},
#endif
{ 0, NULL }
{ 0, 0, NULL }
};
CONST UINTN InitializerCount = ((sizeof (FuncParamsInfo)) / (sizeof (FuncParamsInfo[0])));
@ -2591,6 +2636,12 @@ CONST DISPATCH_TABLE ROMDATA ApDispatchTable[] =
MAKE_DBG_STR (\nCfgLvdsSpreadSpectrum , CFG_GFX_LVDS_SPREAD_SPECTRUM),
MAKE_DBG_STR (\nCfgLvdsSpreadSpectrumRate , CFG_GFX_LVDS_SPREAD_SPECTRUM_RATE),
MAKE_DBG_STR (\nCfgLvdsMiscControl.FpdiMode , CFG_LVDS_MISC_888_FPDI_MODE),
MAKE_DBG_STR (\nCfgLvdsMiscControl.DlChSwap , CFG_LVDS_MISC_DL_CH_SWAP),
MAKE_DBG_STR (\nCfgLvdsMiscControl.VsyncActiveLow , CFG_LVDS_MISC_VSYNC_ACTIVE_LOW),
MAKE_DBG_STR (\nCfgLvdsMiscControl.HsyncActiveLow , CFG_LVDS_MISC_HSYNC_ACTIVE_LOW),
MAKE_DBG_STR (\nCfgLvdsMiscControl.BLONActiveLow , CFG_LVDS_MISC_BLON_ACTIVE_LOW),
MAKE_DBG_STR (\nCfgPcieRefClkSpreadSpectrum , CFG_PCIE_REFCLK_SPREAD_SPECTRUM),
#endif
NULL
};

6
src/vendorcode/amd/agesa/f14/Legacy/Proc/Dispatcher.c
View File

@ -107,7 +107,7 @@ AmdAgesaDispatcher (
// 2. Try next dispatcher if possible, and we have not already got status back
if ((mCpuModuleID.NextBlock != NULL) && (Status == AGESA_UNSUPPORTED)) {
ModuleEntry = (MODULE_ENTRY) (UINT64) mCpuModuleID.NextBlock->ModuleDispatcher;
ModuleEntry = (MODULE_ENTRY) mCpuModuleID.NextBlock->ModuleDispatcher;
if (ModuleEntry != NULL) {
Status = (*ModuleEntry) (ConfigPtr);
}
@ -119,10 +119,10 @@ AmdAgesaDispatcher (
ImageStart = ((AMD_CONFIG_PARAMS *)ConfigPtr)->AltImageBasePtr;
ImageEnd = ImageStart + 4;
// Locate/test image base that matches this component
AltImagePtr = LibAmdLocateImage ((VOID *) (UINT64)ImageStart, (VOID *) (UINT64)ImageEnd, 4096, AGESA_ID);
AltImagePtr = LibAmdLocateImage ((VOID *)ImageStart, (VOID *)ImageEnd, 4096, (CHAR8 *)AGESA_ID);
if (AltImagePtr != NULL) {
//Invoke alternative Image
ImageEntry = (IMAGE_ENTRY) ((UINT64) AltImagePtr + AltImagePtr->EntryPointAddress);
ImageEntry = (IMAGE_ENTRY) (AltImagePtr + AltImagePtr->EntryPointAddress);
Status = (*ImageEntry) (ConfigPtr);
}
}

6
src/vendorcode/amd/agesa/f14/Legacy/Proc/agesaCallouts.c
View File

@ -71,6 +71,12 @@
*----------------------------------------------------------------------------------------
*/
AGESA_STATUS
AgesaGetIdsData (
IN UINTN Data,
IN OUT IDS_CALLOUT_STRUCT *IdsCalloutData
);
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------

17
src/vendorcode/amd/agesa/f14/Legacy/Proc/hobTransfer.c
View File

@ -58,7 +58,8 @@
#include "cpuCacheInit.h"
#include "cpuFamilyTranslation.h"
#include "heapManager.h"
#include "cpuLateInit.h"
//#include "cpuLateInit.h"
#include "cpuEnvInit.h"
#include "Filecode.h"
CODE_GROUP (G1_PEICC)
RDATA_GROUP (G1_PEICC)
@ -179,8 +180,8 @@ CopyHeapToTempRamAtPost (
// Region above 1MB
// Variable MTTR region
// Get family specific cache Info
GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader);
FamilySpecificServices->GetCacheInfo (FamilySpecificServices, &CacheInfoPtr, &Ignored, StdHeader);
GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
FamilySpecificServices->GetCacheInfo (FamilySpecificServices, (const VOID **)&CacheInfoPtr, &Ignored, StdHeader);
// Find an empty MTRRphysBase/MTRRphysMask
for (HeapRamVariableMtrr = AMD_MTRR_VARIABLE_HEAP_BASE;
@ -215,7 +216,7 @@ CopyHeapToTempRamAtPost (
HeapInCacheOffset = HeapManagerInCache->FirstActiveBufferOffset;
HeapInCache = (BUFFER_NODE *) (BaseAddressInCache + HeapInCacheOffset);
BaseAddressInTempMem = (UINT8 *) UserOptions.CfgHeapDramAddress;
BaseAddressInTempMem = (UINT8 *) (UserOptions.CfgHeapDramAddress);
HeapManagerInTempMem = (HEAP_MANAGER *) BaseAddressInTempMem;
HeapInTempMem = (BUFFER_NODE *) (BaseAddressInTempMem + TotalSize);
@ -370,15 +371,15 @@ CopyHeapToMainRamAtPost (
// if address of heap in temp memory is above 1M, then we must used one variable MTRR.
if (StdHeader->HeapBasePtr >= 0x100000) {
// Find out which variable MTRR was used in CopyHeapToTempRamAtPost.
GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader);
FamilySpecificServices->GetCacheInfo (FamilySpecificServices, &CacheInfoPtr, &Ignored, StdHeader);
GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
FamilySpecificServices->GetCacheInfo (FamilySpecificServices, (const VOID **)&CacheInfoPtr, &Ignored, StdHeader);
for (HeapRamVariableMtrr = AMD_MTRR_VARIABLE_HEAP_BASE;
HeapRamVariableMtrr >= AMD_MTRR_VARIABLE_BASE0;
HeapRamVariableMtrr--) {
LibAmdMsrRead (HeapRamVariableMtrr, &VariableMtrrBase, StdHeader);
LibAmdMsrRead ((HeapRamVariableMtrr + 1), &VariableMtrrMask, StdHeader);
if ((VariableMtrrBase == (UINT64) (StdHeader->HeapBasePtr & CacheInfoPtr->HeapBaseMask)) &&
(VariableMtrrMask == (UINT64) (CacheInfoPtr->VariableMtrrHeapMask & AMD_HEAP_MTRR_MASK))) {
if ((VariableMtrrBase == ((UINT64)(StdHeader->HeapBasePtr) & CacheInfoPtr->HeapBaseMask)) &&
(VariableMtrrMask == (CacheInfoPtr->VariableMtrrHeapMask & AMD_HEAP_MTRR_MASK))) {
break;
}
}

25
src/vendorcode/amd/agesa/f14/Legacy/agesa.inc
View File

@ -9,7 +9,7 @@
; * @xrefitem bom "File Content Label" "Release Content"
; * @e project: AGESA
; * @e sub-project: Include
; * @e \$Revision: 41505 $ @e \$Date: 2010-11-05 22:06:20 +0800 (Fri, 05 Nov 2010) $
; * @e \$Revision: 47417 $ @e \$Date: 2011-02-18 12:48:20 -0700 (Fri, 18 Feb 2011) $
;
;*****************************************************************************
;
@ -714,6 +714,23 @@ PCIE_HDP_TYPE TEXTEQU <DWORD>
;----------------------------------------------------------------------------
;
; LVDS Misc Control Field
LVDS_MISC_CONTROL_FIELD STRUCT
FpdiMode UINT8 ?
;IN UINT8 FpdiMode:1;
;IN UINT8 DlChSwap:1;
;IN UINT8 VsyncActiveLow:1;
;IN UINT8 HsyncActiveLow:1;
;IN UINT8 BLONActiveLow:1;
;IN UINT8 Reserved:3;
LVDS_MISC_CONTROL_FIELD ENDS
; LVDS Misc Control
LVDS_MISC_CONTROL UNION
Field LVDS_MISC_CONTROL_FIELD {}
Value UINT8 ?
LVDS_MISC_CONTROL ENDS
; Configuration settings for GNB.
GNB_ENV_CONFIGURATION STRUCT
Gnb3dStereoPinIndex UINT8 ? ;< 3D Stereo Pin ID.
@ -726,6 +743,8 @@ GNB_ENV_CONFIGURATION STRUCT
; @li 6 = Use processor pin HPD6
LvdsSpreadSpectrum UINT16 ? ; Spread spectrum value in 0.01 %
LvdsSpreadSpectrumRate UINT16 ? ; Spread spectrum frequency used by SS hardware logic in unit of 10Hz, 0 - default frequency 40kHz
LvdsMiscControl LVDS_MISC_CONTROL {} ; This item configures LVDS swap/Hsync/Vsync/BLON
PcieRefClkSpreadSpectrum UINT16 ? ; Spread spectrum value in 0.01 %
GNB_ENV_CONFIGURATION ENDS
; GNB configuration info
@ -1916,6 +1935,8 @@ BUILD_OPT_CFG STRUCT
CfgGnbPcieSSID UINT32 ? ; < Gnb PCIe SSID
CfgLvdsSpreadSpectrum UINT16 ? ; < Lvds Spread Spectrum. Build-time customizable only
CfgLvdsSpreadSpectrumRate UINT16 ? ; < Lvds Spread Spectrum Rate. Build-time customizable only
CfgLvdsMiscControl LVDS_MISC_CONTROL {}; THe LVDS Misc control
CfgPcieRefClkSpreadSpectrum UINT16 ? ; PCIe Reference Clock Spread Spectrum
Reserved BOOLEAN ? ; < reserved...
BUILD_OPT_CFG ENDS
@ -2143,6 +2164,7 @@ TYPE17_DMI_INFO STRUCT
PartNumber CHAR8 (19) DUP (?) ; < Part Number.
Attributes UINT8 ? ; < Bits 7-4: Reserved, Bits 3-0: rank.
ExtSize UINT32 ? ; < Extended Size.
ConfigSpeed UINT16 ? ; < Configured memory clock speed
TYPE17_DMI_INFO ENDS
; Memory DMI Type 17 and 20 - for memory use
@ -2169,6 +2191,7 @@ MEM_DMI_INFO STRUCT
EndingAddr UINT32 ? ; ///< The handle, or instance number, associated with
; ///< the Memory Device structure to which this address
; ///< range is mapped.
ConfigSpeed UINT16 ? ; ///< Configured memory clock speed
MEM_DMI_INFO ENDS
; DMI Type 19 - Memory Array Mapped Address

2
src/vendorcode/amd/agesa/f14/Lib/amdlib.c
View File

@ -9,7 +9,7 @@
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Lib
* @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
* @e \$Revision: 44325 $ @e \$Date: 2010-12-22 03:29:53 -0700 (Wed, 22 Dec 2010) $
*
*/
/*

23
src/vendorcode/amd/agesa/f14/Makefile.inc
View File

@ -2,7 +2,7 @@
#
# Copyright (c) 2011, Advanced Micro Devices, Inc.
# All rights reserved.
#
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are met:
# * Redistributions of source code must retain the above copyright
@ -13,7 +13,7 @@
# * Neither the name of Advanced Micro Devices, Inc. nor the names of
# its contributors may be used to endorse or promote products derived
# from this software without specific prior written permission.
#
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@ -24,7 +24,7 @@
# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
#
#*****************************************************************************
# AGESA V5 Files
@ -36,19 +36,16 @@ AGESA_INC += -I$(AGESA_ROOT)/Include
AGESA_INC += -I$(AGESA_ROOT)/Lib
AGESA_INC += -I$(AGESA_ROOT)/Legacy
AGESA_INC += -I$(AGESA_ROOT)/Proc/Common
AGESA_INC += -I$(AGESA_ROOT)/Proc/HT
AGESA_INC += -I$(AGESA_ROOT)/Proc/CPU
AGESA_INC += -I$(AGESA_ROOT)/Proc/CPU/Feature
AGESA_INC += -I$(AGESA_ROOT)/Proc/CPU/Family
AGESA_INC += -I$(AGESA_ROOT)/Proc/CPU/Family/0x14
AGESA_INC += -I$(AGESA_ROOT)/Proc/CPU/Family/0x14/ON
AGESA_INC += -I$(AGESA_ROOT)/Proc/Mem
AGESA_INC += -I$(AGESA_ROOT)/Proc/Mem/NB/ON
AGESA_INC += -I$(AGESA_ROOT)/Proc/IDS
AGESA_INC += -I$(AGESA_ROOT)/Proc/IDS/Family
AGESA_INC += -I$(AGESA_ROOT)/Proc/IDS/Family/0x14
AGESA_INC += -I$(AGESA_ROOT)/Proc/CPU/Feature
AGESA_INC += -I$(AGESA_ROOT)/Proc/GNB
AGESA_INC += -I$(AGESA_ROOT)/Proc/GNB/Common
AGESA_INC += -I$(AGESA_ROOT)/Proc/GNB/Gfx
AGESA_INC += -I$(AGESA_ROOT)/Proc/GNB/Gfx/Family
AGESA_INC += -I$(AGESA_ROOT)/Proc/GNB/Modules/GnbCommonLib
AGESA_INC += -I$(AGESA_ROOT)/Proc/GNB/Nb
AGESA_INC += -I$(AGESA_ROOT)/Proc/GNB/Nb/Family
AGESA_INC += -I$(AGESA_ROOT)/Proc/GNB/Nb/Family/0x14
@ -57,8 +54,10 @@ AGESA_INC += -I$(AGESA_ROOT)/Proc/GNB/PCIe
AGESA_INC += -I$(AGESA_ROOT)/Proc/GNB/PCIe/Family
AGESA_INC += -I$(AGESA_ROOT)/Proc/GNB/PCIe/Family/0x14
AGESA_INC += -I$(AGESA_ROOT)/Proc/GNB/PCIe/Feature
AGESA_INC += -I$(AGESA_ROOT)/Proc/GNB/Gfx
AGESA_INC += -I$(AGESA_ROOT)/Proc/GNB/Gfx/Family
AGESA_INC += -I$(AGESA_ROOT)/Proc/HT
AGESA_INC += -I$(AGESA_ROOT)/Proc/IDS
AGESA_INC += -I$(AGESA_ROOT)/Proc/Mem
AGESA_INC += -I$(AGESA_ROOT)/Proc/Mem/NB/ON
AGESA_INC += -I$(AGESA_ROOT)/Proc/Recovery/GNB
AGESA_INC += -I$(AGESA_ROOT)/Proc/Recovery/CPU
AGESA_INC += -I$(AGESA_ROOT)/Proc/Recovery/Mem

5
src/vendorcode/amd/agesa/f14/Porting.h
View File

@ -226,6 +226,7 @@
#define VOLATILE volatile
#define TRUE 1
#define FALSE 0
// #undef CONST
#define CONST const
#define ROMDATA
#define CALLCONV
@ -267,10 +268,6 @@
#ifndef NULL
#define NULL (void *)0
#endif
#ifdef ROMDATA
//#undef ROMDATA
#endif
//#define ROMDATA __attribute__ ((section("rom.data"))
#else
// -----------------------------------------------------------------------

14
src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/F10IoCstate.c
View File

@ -108,19 +108,19 @@ F10InitializeIoCstate (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT64 MsrRegister;
UINT64 MsrReg;
AP_TASK TaskPtr;
if ((EntryPoint & CPU_FEAT_AFTER_PM_INIT) != 0) {
// Initialize MSRC001_0073[CstateAddr] on each core to a region of
// the IO address map with 8 consecutive available addresses.
MsrRegister = 0;
MsrReg = 0;
((CSTATE_ADDRESS_MSR *) &MsrRegister)->CstateAddr = PlatformConfig->CStateIoBaseAddress;
((CSTATE_ADDRESS_MSR *) &MsrReg)->CstateAddr = PlatformConfig->CStateIoBaseAddress;
TaskPtr.FuncAddress.PfApTaskI = F10InitializeIoCstateOnCore;
TaskPtr.DataTransfer.DataSizeInDwords = 2;
TaskPtr.DataTransfer.DataPtr = &MsrRegister;
TaskPtr.DataTransfer.DataPtr = &MsrReg;
TaskPtr.DataTransfer.DataTransferFlags = 0;
TaskPtr.ExeFlags = WAIT_FOR_CORE;
ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, NULL);
@ -264,7 +264,7 @@ F10IsIoCstateFeatureSupported (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT64 MsrRegister;
UINT64 MsrReg;
CPUID_DATA CpuId;
CPU_LOGICAL_ID LogicalId;
@ -274,8 +274,8 @@ F10IsIoCstateFeatureSupported (
if ((LogicalId.Revision & AMD_F10_Ex) != 0) {
LibAmdCpuidRead (AMD_CPUID_APM, &CpuId, StdHeader);
if (((CpuId.EDX_Reg & 0x00000200) >> 9) == 1) {
LibAmdMsrRead (MSR_PATCH_LEVEL, &MsrRegister, StdHeader);
if ((MsrRegister & 0xffffffff) >= 0x010000BF) {
LibAmdMsrRead (MSR_PATCH_LEVEL, &MsrReg, StdHeader);
if ((MsrReg & 0xffffffff) >= 0x010000BF) {
return TRUE;
}
}

30
src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/F10PmNbCofVidInit.c
View File

@ -250,16 +250,16 @@ PmNbCofVidInitP0P1Core (
)
{
UINT32 MsrAddress;
UINT64 MsrRegister;
UINT64 MsrReg;
CPU_SPECIFIC_SERVICES *FamilySpecificServices;
GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader);
LibAmdMsrRead (MSR_COFVID_STS, &MsrRegister, StdHeader);
MsrAddress = (UINT32) ((((COFVID_STS_MSR *) &MsrRegister)->StartupPstate) + PS_REG_BASE);
LibAmdMsrRead (MsrAddress, &MsrRegister, StdHeader);
LibAmdMsrWrite ((UINT32) (PS_REG_BASE + 1), &MsrRegister, StdHeader);
((PSTATE_MSR *) &MsrRegister)->NbVid = *(UINT8 *) NewNbVid;
LibAmdMsrWrite (PS_REG_BASE, &MsrRegister, StdHeader);
GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
LibAmdMsrRead (MSR_COFVID_STS, &MsrReg, StdHeader);
MsrAddress = (UINT32) ((((COFVID_STS_MSR *) &MsrReg)->StartupPstate) + PS_REG_BASE);
LibAmdMsrRead (MsrAddress, &MsrReg, StdHeader);
LibAmdMsrWrite ((UINT32) (PS_REG_BASE + 1), &MsrReg, StdHeader);
((PSTATE_MSR *) &MsrReg)->NbVid = *(UINT8 *) NewNbVid;
LibAmdMsrWrite (PS_REG_BASE, &MsrReg, StdHeader);
FamilySpecificServices->TransitionPstate (FamilySpecificServices, (UINT8) 1, (BOOLEAN) FALSE, StdHeader);
}
@ -283,16 +283,16 @@ PmNbCofVidInitWarmCore (
)
{
UINT32 MsrAddress;
UINT64 MsrRegister;
UINT64 MsrReg;
CPU_SPECIFIC_SERVICES *FamilySpecificServices;
GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader);
GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
for (MsrAddress = PS_REG_BASE; MsrAddress <= PS_MAX_REG; MsrAddress++) {
LibAmdMsrRead (MsrAddress, &MsrRegister, StdHeader);
if (((PSTATE_MSR *) &MsrRegister)->IddValue != 0) {
if ((((PSTATE_MSR *) &MsrRegister)->NbDid == 0) || ((NB_COF_VID_INIT_WARM *) FunctionData)->NbVidUpdateAll) {
((PSTATE_MSR *) &MsrRegister)->NbVid = ((NB_COF_VID_INIT_WARM *) FunctionData)->NewNbVid;
LibAmdMsrWrite (MsrAddress, &MsrRegister, StdHeader);
LibAmdMsrRead (MsrAddress, &MsrReg, StdHeader);
if (((PSTATE_MSR *) &MsrReg)->IddValue != 0) {
if ((((PSTATE_MSR *) &MsrReg)->NbDid == 0) || ((NB_COF_VID_INIT_WARM *) FunctionData)->NbVidUpdateAll) {
((PSTATE_MSR *) &MsrReg)->NbVid = ((NB_COF_VID_INIT_WARM *) FunctionData)->NewNbVid;
LibAmdMsrWrite (MsrAddress, &MsrReg, StdHeader);
}
}
}

12
src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/F10PmNbPstateInit.c
View File

@ -174,14 +174,14 @@ PmNbPstateInitCore (
)
{
UINT32 MsrAddress;
UINT64 MsrRegister;
UINT64 MsrReg;
for (MsrAddress = (PS_REG_BASE + ((NB_PSTATE_INIT *) NbPstateParams)->NbPstate); MsrAddress <= PS_MAX_REG; MsrAddress++) {
LibAmdMsrRead (MsrAddress, &MsrRegister, StdHeader);
if (((PSTATE_MSR *) &MsrRegister)->PsEnable == 1) {
((PSTATE_MSR *) &MsrRegister)->NbDid = 1;
((PSTATE_MSR *) &MsrRegister)->NbVid = ((NB_PSTATE_INIT *) NbPstateParams)->NbVid1;
LibAmdMsrWrite (MsrAddress, &MsrRegister, StdHeader);
LibAmdMsrRead (MsrAddress, &MsrReg, StdHeader);
if (((PSTATE_MSR *) &MsrReg)->PsEnable == 1) {
((PSTATE_MSR *) &MsrReg)->NbDid = 1;
((PSTATE_MSR *) &MsrReg)->NbVid = ((NB_PSTATE_INIT *) NbPstateParams)->NbVid1;
LibAmdMsrWrite (MsrAddress, &MsrReg, StdHeader);
}
}
}

22
src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevC/F10RevCHwC1e.c
View File

@ -134,18 +134,18 @@ F10InitializeHwC1e (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT64 MsrRegister;
UINT64 MsrReg;
AP_TASK TaskPtr;
MsrRegister = 0;
((INTPEND_MSR *) &MsrRegister)->IoMsgAddr = PlatformConfig->C1ePlatformData;
((INTPEND_MSR *) &MsrRegister)->IoRd = 1;
((INTPEND_MSR *) &MsrRegister)->C1eOnCmpHalt = 1;
((INTPEND_MSR *) &MsrRegister)->SmiOnCmpHalt = 0;
MsrReg = 0;
((INTPEND_MSR *) &MsrReg)->IoMsgAddr = PlatformConfig->C1ePlatformData;
((INTPEND_MSR *) &MsrReg)->IoRd = 1;
((INTPEND_MSR *) &MsrReg)->C1eOnCmpHalt = 1;
((INTPEND_MSR *) &MsrReg)->SmiOnCmpHalt = 0;
TaskPtr.FuncAddress.PfApTaskI = F10InitializeHwC1eOnCore;
TaskPtr.DataTransfer.DataSizeInDwords = 2;
TaskPtr.DataTransfer.DataPtr = &MsrRegister;
TaskPtr.DataTransfer.DataPtr = &MsrReg;
TaskPtr.DataTransfer.DataTransferFlags = 0;
TaskPtr.ExeFlags = WAIT_FOR_CORE;
ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, NULL);
@ -168,16 +168,16 @@ F10InitializeHwC1eOnCore (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT64 MsrRegister;
UINT64 MsrReg;
// Enable C1e
LibAmdMsrWrite (MSR_INTPEND, (UINT64 *) IntPendMsr, StdHeader);
// Set OS Visible Workaround Status BIT1 to indicate that C1e
// is enabled.
LibAmdMsrRead (MSR_OSVW_Status, &MsrRegister, StdHeader);
MsrRegister |= BIT1;
LibAmdMsrWrite (MSR_OSVW_Status, &MsrRegister, StdHeader);
LibAmdMsrRead (MSR_OSVW_Status, &MsrReg, StdHeader);
MsrReg |= BIT1;
LibAmdMsrWrite (MSR_OSVW_Status, &MsrReg, StdHeader);
}

24
src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevC/F10RevCSwC1e.c
View File

@ -126,19 +126,19 @@ F10InitializeSwC1e (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT64 MsrRegister;
UINT64 MsrReg;
AP_TASK TaskPtr;
MsrRegister = 0;
((INTPEND_MSR *) &MsrRegister)->IoMsgAddr = PlatformConfig->C1ePlatformData1;
((INTPEND_MSR *) &MsrRegister)->IoMsgData = PlatformConfig->C1ePlatformData2;
((INTPEND_MSR *) &MsrRegister)->IoRd = 0;
((INTPEND_MSR *) &MsrRegister)->C1eOnCmpHalt = 0;
((INTPEND_MSR *) &MsrRegister)->SmiOnCmpHalt = 1;
MsrReg = 0;
((INTPEND_MSR *) &MsrReg)->IoMsgAddr = PlatformConfig->C1ePlatformData1;
((INTPEND_MSR *) &MsrReg)->IoMsgData = PlatformConfig->C1ePlatformData2;
((INTPEND_MSR *) &MsrReg)->IoRd = 0;
((INTPEND_MSR *) &MsrReg)->C1eOnCmpHalt = 0;
((INTPEND_MSR *) &MsrReg)->SmiOnCmpHalt = 1;
TaskPtr.FuncAddress.PfApTaskI = F10InitializeSwC1eOnCore;
TaskPtr.DataTransfer.DataSizeInDwords = 2;
TaskPtr.DataTransfer.DataPtr = &MsrRegister;
TaskPtr.DataTransfer.DataPtr = &MsrReg;
TaskPtr.DataTransfer.DataTransferFlags = 0;
TaskPtr.ExeFlags = WAIT_FOR_CORE;
ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, NULL);
@ -161,16 +161,16 @@ F10InitializeSwC1eOnCore (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT64 MsrRegister;
UINT64 MsrReg;
// Enable C1e
LibAmdMsrWrite (MSR_INTPEND, (UINT64 *) IntPendMsr, StdHeader);
// Set OS Visible Workaround Status BIT1 to indicate that C1e
// is enabled.
LibAmdMsrRead (MSR_OSVW_Status, &MsrRegister, StdHeader);
MsrRegister |= BIT1;
LibAmdMsrWrite (MSR_OSVW_Status, &MsrRegister, StdHeader);
LibAmdMsrRead (MSR_OSVW_Status, &MsrReg, StdHeader);
MsrReg |= BIT1;
LibAmdMsrWrite (MSR_OSVW_Status, &MsrReg, StdHeader);
}

6
src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevC/F10RevCUtilities.c
View File

@ -320,7 +320,7 @@ F10CommonRevCGetNbPstateInfo (
UINT32 NbVid;
UINT32 PciRegister;
UINT32 ProductInfoRegister;
UINT64 MsrRegister;
UINT64 MsrReg;
BOOLEAN PstateIsValid;
PstateIsValid = TRUE;
@ -339,8 +339,8 @@ F10CommonRevCGetNbPstateInfo (
PciAddress->Address.Register = CPTC0_REG;
LibAmdPciRead (AccessWidth32, *PciAddress, &PciRegister, StdHeader);
NbFid = ((CLK_PWR_TIMING_CTRL_REGISTER *) &PciRegister)->NbFid;
LibAmdMsrRead (MSR_COFVID_STS, &MsrRegister, StdHeader);
NbVid = (UINT32) ((COFVID_STS_MSR *) &MsrRegister)->CurNbVid;
LibAmdMsrRead (MSR_COFVID_STS, &MsrReg, StdHeader);
NbVid = (UINT32) ((COFVID_STS_MSR *) &MsrReg)->CurNbVid;
} else {
NbFid = ((PRODUCT_INFO_REGISTER *) &ProductInfoRegister)->SinglePlaneNbFid;
NbVid = ((PRODUCT_INFO_REGISTER *) &ProductInfoRegister)->SinglePlaneNbVid;

8
src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevD/F10RevDHtAssist.c
View File

@ -324,11 +324,11 @@ F10HookDisableCache (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT64 MsrRegister;
UINT64 MsrReg;
LibAmdMsrRead (MSR_BU_CFG2, &MsrRegister, StdHeader);
MsrRegister |= BIT42;
LibAmdMsrWrite (MSR_BU_CFG2, &MsrRegister, StdHeader);
LibAmdMsrRead (MSR_BU_CFG2, &MsrReg, StdHeader);
MsrReg |= BIT42;
LibAmdMsrWrite (MSR_BU_CFG2, &MsrReg, StdHeader);
}

24
src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevD/F10RevDMsgBasedC1e.c
View File

@ -225,22 +225,22 @@ F10InitializeMsgBasedC1eOnCore (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT64 MsrRegister;
UINT64 MsrReg;
// Set MSRC001_0055[SmiOnCmpHalt] = 0, MSRC001_0055[C1eOnCmpHalt] = 0
LibAmdMsrRead (MSR_INTPEND, &MsrRegister, StdHeader);
((INTPEND_MSR *) &MsrRegister)->SmiOnCmpHalt = 0;
((INTPEND_MSR *) &MsrRegister)->C1eOnCmpHalt = 0;
((INTPEND_MSR *) &MsrRegister)->BmStsClrOnHltEn = 1;
((INTPEND_MSR *) &MsrRegister)->IntrPndMsgDis = 0;
((INTPEND_MSR *) &MsrRegister)->IntrPndMsg = 0;
((INTPEND_MSR *) &MsrRegister)->IoMsgAddr = (UINT64) *((UINT32 *) BmStsAddress);
LibAmdMsrWrite (MSR_INTPEND, &MsrRegister, StdHeader);
LibAmdMsrRead (MSR_INTPEND, &MsrReg, StdHeader);
((INTPEND_MSR *) &MsrReg)->SmiOnCmpHalt = 0;
((INTPEND_MSR *) &MsrReg)->C1eOnCmpHalt = 0;
((INTPEND_MSR *) &MsrReg)->BmStsClrOnHltEn = 1;
((INTPEND_MSR *) &MsrReg)->IntrPndMsgDis = 0;
((INTPEND_MSR *) &MsrReg)->IntrPndMsg = 0;
((INTPEND_MSR *) &MsrReg)->IoMsgAddr = (UINT64) *((UINT32 *) BmStsAddress);
LibAmdMsrWrite (MSR_INTPEND, &MsrReg, StdHeader);
// Set MSRC001_0015[HltXSpCycEn] = 1
LibAmdMsrRead (MSR_HWCR, &MsrRegister, StdHeader);
MsrRegister |= BIT12;
LibAmdMsrWrite (MSR_HWCR, &MsrRegister, StdHeader);
LibAmdMsrRead (MSR_HWCR, &MsrReg, StdHeader);
MsrReg |= BIT12;
LibAmdMsrWrite (MSR_HWCR, &MsrReg, StdHeader);
}
/*---------------------------------------------------------------------------------------*/

6
src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevD/F10RevDUtilities.c
View File

@ -309,7 +309,7 @@ F10CommonRevDGetNbPstateInfo (
)
{
UINT32 PciRegister;
UINT64 MsrRegister;
UINT64 MsrReg;
BOOLEAN PstateIsValid;
PstateIsValid = FALSE;
@ -319,8 +319,8 @@ F10CommonRevDGetNbPstateInfo (
LibAmdPciRead (AccessWidth32, *PciAddress, &PciRegister, StdHeader);
*FreqNumeratorInMHz = ((((CLK_PWR_TIMING_CTRL_REGISTER *) &PciRegister)->NbFid + 4) * 200);
*FreqDivisor = 1;
LibAmdMsrRead (MSR_COFVID_STS, &MsrRegister, StdHeader);
*VoltageInuV = (1550000 - (12500 * ((UINT32) ((COFVID_STS_MSR *) &MsrRegister)->CurNbVid)));
LibAmdMsrRead (MSR_COFVID_STS, &MsrReg, StdHeader);
*VoltageInuV = (1550000 - (12500 * ((UINT32) ((COFVID_STS_MSR *) &MsrReg)->CurNbVid)));
PstateIsValid = TRUE;
}
return PstateIsValid;

18
src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevD/HY/F10HyMsrTables.c
View File

@ -87,12 +87,12 @@ STATIC CONST MSR_TYPE_ENTRY_INITIALIZER ROMDATA F10HyMsrRegisters[] =
AMD_FAMILY_10, // CpuFamily
AMD_F10_GT_B0 // CpuRevision
},
AMD_PF_ALL, // platformFeatures
{
{AMD_PF_ALL}, // platformFeatures
{{
MSR_LS_CFG, // MSR Address
0x0000000000000000, // OR Mask
(1 << 1) // NAND Mask
}
}}
},
// MSR_BU_CFG (0xC0011023)
@ -103,12 +103,12 @@ STATIC CONST MSR_TYPE_ENTRY_INITIALIZER ROMDATA F10HyMsrRegisters[] =
AMD_FAMILY_10, // CpuFamily
AMD_F10_GT_B0 // CpuRevision
},
AMD_PF_ALL, // platformFeatures
{
{AMD_PF_ALL}, // platformFeatures
{{
MSR_BU_CFG, // MSR Address
(1 << 21), // OR Mask
(1 << 21), // NAND Mask
}
}}
},
// MSR_BU_CFG2 (0xC001102A)
@ -120,12 +120,12 @@ STATIC CONST MSR_TYPE_ENTRY_INITIALIZER ROMDATA F10HyMsrRegisters[] =
AMD_FAMILY_10, // CpuFamily
AMD_F10_GT_C0 // CpuRevision
},
AMD_PF_ALL, // platformFeatures
{
{AMD_PF_ALL}, // platformFeatures
{{
MSR_BU_CFG2, // MSR Address
0x0004000000000000, // OR Mask
0x0004000000000000, // NAND Mask
}
}}
}
};

6
src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevE/F10RevEUtilities.c
View File

@ -285,7 +285,7 @@ F10CommonRevEGetNbPstateInfo (
)
{
UINT32 PciRegister;
UINT64 MsrRegister;
UINT64 MsrReg;
BOOLEAN PstateIsValid;
PstateIsValid = FALSE;
@ -295,8 +295,8 @@ F10CommonRevEGetNbPstateInfo (
LibAmdPciRead (AccessWidth32, *PciAddress, &PciRegister, StdHeader);
*FreqNumeratorInMHz = ((((CLK_PWR_TIMING_CTRL_REGISTER *) &PciRegister)->NbFid + 4) * 200);
*FreqDivisor = 1;
LibAmdMsrRead (MSR_COFVID_STS, &MsrRegister, StdHeader);
*VoltageInuV = (1550000 - (12500 * ((UINT32) ((COFVID_STS_MSR *) &MsrRegister)->CurNbVid)));
LibAmdMsrRead (MSR_COFVID_STS, &MsrReg, StdHeader);
*VoltageInuV = (1550000 - (12500 * ((UINT32) ((COFVID_STS_MSR *) &MsrReg)->CurNbVid)));
PstateIsValid = TRUE;
}
return PstateIsValid;

4
src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10Dmi.c
View File

@ -122,7 +122,7 @@ DmiF10GetInfo (
CpuInfoPtr->BrandId.Model = (UINT8) (CpuId.EBX_Reg >> 4) & 0x7F; // bit 10:4
CpuInfoPtr->BrandId.String2 = (UINT8) (CpuId.EBX_Reg & 0xF); // bit 3:0
GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader);
GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
CpuInfoPtr->TotalCoreNumber = FamilySpecificServices->GetNumberOfCoresForBrandstring (FamilySpecificServices, StdHeader);
CpuInfoPtr->TotalCoreNumber--;
@ -239,7 +239,7 @@ DmiF10GetMaxSpeed (
PSTATE_CPU_FAMILY_SERVICES *FamilyServices;
FamilyServices = NULL;
GetFeatureServicesOfCurrentCore (&PstateFamilyServiceTable, &FamilyServices, StdHeader);
GetFeatureServicesOfCurrentCore (&PstateFamilyServiceTable, (const VOID **)&FamilyServices, StdHeader);
ASSERT (FamilyServices != NULL);
NumBoostStates = 0;
LibAmdCpuidRead (AMD_CPUID_APM, &CpuidData, StdHeader);

58
src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10EarlyInit.c
View File

@ -165,7 +165,7 @@ F10PmAfterReset (
UINT32 Core;
UINT32 AndMask;
UINT32 OrMask;
UINT64 MsrRegister;
UINT64 MsrReg;
PCI_ADDR PciAddress;
AP_TASK TaskPtr;
AGESA_STATUS IgnoredSts;
@ -179,8 +179,8 @@ F10PmAfterReset (
// Step 1 Modify F3xDC[PstateMaxVal] to reflect the lowest performance
// P-state supported, as indicated in MSRC001_00[68:64][PstateEn]
for (MsrAddr = PS_MAX_REG; MsrAddr > PS_REG_BASE; --MsrAddr) {
LibAmdMsrRead (MsrAddr, &MsrRegister, StdHeader);
if (((PSTATE_MSR *) &MsrRegister)->PsEnable == 1) {
LibAmdMsrRead (MsrAddr, &MsrReg, StdHeader);
if (((PSTATE_MSR *) &MsrReg)->PsEnable == 1) {
break;
}
}
@ -227,7 +227,7 @@ F10PmAfterResetCore (
UINT32 Ignored;
UINT32 PsMaxVal;
UINT32 PciRegister;
UINT64 MsrRegister;
UINT64 MsrReg;
UINT64 SavedMsr;
UINT64 CurrentLimitMsr;
PCI_ADDR PciAddress;
@ -238,13 +238,13 @@ F10PmAfterResetCore (
// Step 2 If MSR C001_0071[CurNbDid] = 0, set MSR C001_001F[GfxNbPstateDis]
GetLogicalIdOfCurrentCore (&LogicalId, StdHeader);
GetCpuServicesFromLogicalId (&LogicalId, &FamilySpecificServices, StdHeader);
GetCpuServicesFromLogicalId (&LogicalId, (const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
if ((LogicalId.Revision & (AMD_F10_C3 | AMD_F10_DA_C2)) != 0) {
LibAmdMsrRead (MSR_COFVID_STS, &MsrRegister, StdHeader);
if (((COFVID_STS_MSR *) &MsrRegister)->CurNbDid == 0) {
LibAmdMsrRead (NB_CFG, &MsrRegister, StdHeader);
MsrRegister |= BIT62;
LibAmdMsrWrite (NB_CFG, &MsrRegister, StdHeader);
LibAmdMsrRead (MSR_COFVID_STS, &MsrReg, StdHeader);
if (((COFVID_STS_MSR *) &MsrReg)->CurNbDid == 0) {
LibAmdMsrRead (NB_CFG, &MsrReg, StdHeader);
MsrReg |= BIT62;
LibAmdMsrWrite (NB_CFG, &MsrReg, StdHeader);
}
}
@ -254,8 +254,8 @@ F10PmAfterResetCore (
PsMaxVal = (UINT32) (((PSTATE_CURLIM_MSR *) &CurrentLimitMsr)->PstateMaxVal);
// Step 3 If MSRC001_0071[CurPstate] != F3xDC[PstateMaxVal], go to step 20
LibAmdMsrRead (MSR_COFVID_STS, &MsrRegister, StdHeader);
if (((COFVID_STS_MSR *) &MsrRegister)->CurPstate !=
LibAmdMsrRead (MSR_COFVID_STS, &MsrReg, StdHeader);
if (((COFVID_STS_MSR *) &MsrReg)->CurPstate !=
((PSTATE_CURLIM_MSR *) &CurrentLimitMsr)->PstateMaxVal) {
GoToStep = STEP20;
} else {
@ -282,8 +282,8 @@ F10PmAfterResetCore (
// Step 7 Copy the P-state register pointed to by F3xDC[PstateMaxVal] to the P-state
// register pointed to by F3xDC[PstateMaxVal]+1
LibAmdMsrRead ((MSR_PSTATE_0 + PsMaxVal), &MsrRegister, StdHeader);
LibAmdMsrWrite ((MSR_PSTATE_0 + (PsMaxVal + 1)), &MsrRegister, StdHeader);
LibAmdMsrRead ((MSR_PSTATE_0 + PsMaxVal), &MsrReg, StdHeader);
LibAmdMsrWrite ((MSR_PSTATE_0 + (PsMaxVal + 1)), &MsrReg, StdHeader);
// Step 8 Write F3xDC[PstateMaxVal]+1 to F3xDC[PstateMaxVal]
IdentifyCore (StdHeader, &Socket, &Module, &Ignored, &IgnoredSts);
@ -310,11 +310,11 @@ F10PmAfterResetCore (
// Step 13 If MSRC001_0071[CurNbDid] = 1, set MSRC001_001F[GfxNbPstateDis]
if ((LogicalId.Revision & (AMD_F10_C3 | AMD_F10_DA_C2)) != 0) {
LibAmdMsrRead (MSR_COFVID_STS, &MsrRegister, StdHeader);
if (((COFVID_STS_MSR *) &MsrRegister)->CurNbDid == 1) {
LibAmdMsrRead (NB_CFG, &MsrRegister, StdHeader);
MsrRegister |= BIT62;
LibAmdMsrWrite (NB_CFG, &MsrRegister, StdHeader);
LibAmdMsrRead (MSR_COFVID_STS, &MsrReg, StdHeader);
if (((COFVID_STS_MSR *) &MsrReg)->CurNbDid == 1) {
LibAmdMsrRead (NB_CFG, &MsrReg, StdHeader);
MsrReg |= BIT62;
LibAmdMsrWrite (NB_CFG, &MsrReg, StdHeader);
}
}
@ -343,11 +343,11 @@ F10PmAfterResetCore (
// Step 19 If MSR C001_0071[CurNbDid] = 0, set MSR C001_001F[GfxNbPstateDis]
if ((LogicalId.Revision & (AMD_F10_C3 | AMD_F10_DA_C2)) != 0) {
LibAmdMsrRead (MSR_COFVID_STS, &MsrRegister, StdHeader);
if (((COFVID_STS_MSR *) &MsrRegister)->CurNbDid == 0) {
LibAmdMsrRead (NB_CFG, &MsrRegister, StdHeader);
MsrRegister |= BIT62;
LibAmdMsrWrite (NB_CFG, &MsrRegister, StdHeader);
LibAmdMsrRead (MSR_COFVID_STS, &MsrReg, StdHeader);
if (((COFVID_STS_MSR *) &MsrReg)->CurNbDid == 0) {
LibAmdMsrRead (NB_CFG, &MsrReg, StdHeader);
MsrReg |= BIT62;
LibAmdMsrWrite (NB_CFG, &MsrReg, StdHeader);
}
}
@ -363,11 +363,11 @@ F10PmAfterResetCore (
// Step 22 If MSR C001_0071[CurNbDid] = 1, set MSR C001_001F[GfxNbPstateDis] and exit
// the sequence
if ((LogicalId.Revision & (AMD_F10_C3 | AMD_F10_DA_C2)) != 0) {
LibAmdMsrRead (MSR_COFVID_STS, &MsrRegister, StdHeader);
if (((COFVID_STS_MSR *) &MsrRegister)->CurNbDid == 1) {
LibAmdMsrRead (NB_CFG, &MsrRegister, StdHeader);
MsrRegister |= BIT62;
LibAmdMsrWrite (NB_CFG, &MsrRegister, StdHeader);
LibAmdMsrRead (MSR_COFVID_STS, &MsrReg, StdHeader);
if (((COFVID_STS_MSR *) &MsrReg)->CurNbDid == 1) {
LibAmdMsrRead (NB_CFG, &MsrReg, StdHeader);
MsrReg |= BIT62;
LibAmdMsrWrite (NB_CFG, &MsrReg, StdHeader);
break;
}
}

20
src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10PowerCheck.c
View File

@ -168,7 +168,7 @@ F10PmPwrCheck (
UINT32 OrMask;
UINT32 PstateLimit;
PCI_ADDR PciAddress;
UINT64 MsrRegister;
UINT64 MsrReg;
AP_TASK TaskPtr;
CPUID_DATA CpuidData;
AGESA_STATUS IgnoredSts;
@ -182,8 +182,8 @@ F10PmPwrCheck (
// get the Max P-state value
for (PsMaxVal = NM_PS_REG - 1; PsMaxVal != 0; --PsMaxVal) {
LibAmdMsrRead (PS_REG_BASE + PsMaxVal, &MsrRegister, StdHeader);
if (((PSTATE_MSR *) &MsrRegister)->PsEnable == 1) {
LibAmdMsrRead (PS_REG_BASE + PsMaxVal, &MsrReg, StdHeader);
if (((PSTATE_MSR *) &MsrReg)->PsEnable == 1) {
break;
}
}
@ -331,17 +331,17 @@ F10PmPwrCheckCore (
UINT8 DisPsNum;
UINT8 CurrentPs;
UINT8 EnBsNum;
UINT64 MsrRegister;
UINT64 MsrReg;
CPU_SPECIFIC_SERVICES *FamilySpecificServices;
GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader);
GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
PsMaxVal = (((PWRCHK_ERROR_DATA *) ErrorData)->HwPstateNumber - 1);
DisPsNum = (((PWRCHK_ERROR_DATA *) ErrorData)->HwPstateNumber -
((PWRCHK_ERROR_DATA *) ErrorData)->AllowablePstateNumber);
EnBsNum = ((PWRCHK_ERROR_DATA *) ErrorData)->NumberofBoostStates;
LibAmdMsrRead (MSR_PSTATE_STS, &MsrRegister, StdHeader);
CurrentPs = (UINT8) (((PSTATE_STS_MSR *) &MsrRegister)->CurPstate);
LibAmdMsrRead (MSR_PSTATE_STS, &MsrReg, StdHeader);
CurrentPs = (UINT8) (((PSTATE_STS_MSR *) &MsrReg)->CurPstate);
if (((PWRCHK_ERROR_DATA *) ErrorData)->AllowablePstateNumber == 0) {
@ -413,9 +413,9 @@ F10PmPwrChkCopyPstate (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT64 MsrRegister;
UINT64 MsrReg;
LibAmdMsrRead ((UINT32) (PS_REG_BASE + Src), &MsrRegister, StdHeader);
LibAmdMsrWrite ((UINT32) (PS_REG_BASE + Dest), &MsrRegister, StdHeader);
LibAmdMsrRead ((UINT32) (PS_REG_BASE + Src), &MsrReg, StdHeader);
LibAmdMsrWrite ((UINT32) (PS_REG_BASE + Dest), &MsrReg, StdHeader);
}

40
src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10PowerPlane.c
View File

@ -183,7 +183,7 @@ F10CpuAmdPmPwrPlaneInit (
UINT32 AndMask;
UINT32 OrMask;
UINT32 ProcessorPackageType;
UINT64 MsrRegister;
UINT64 MsrReg;
AP_TASK TaskPtr;
AGESA_STATUS IgnoredSts;
PLATFORM_FEATS Features;
@ -266,10 +266,10 @@ F10CpuAmdPmPwrPlaneInit (
OrMask = 0x00000000;
((POPUP_PSTATE_REGISTER *) &OrMask)->PopupEn = 0;
((POPUP_PSTATE_REGISTER *) &OrMask)->PopupPstate = ((CLK_PWR_TIMING_CTRL2_REGISTER *) &PciRegister)->PstateMaxVal;
LibAmdMsrRead ((((CLK_PWR_TIMING_CTRL2_REGISTER *) &PciRegister)->PstateMaxVal + PS_REG_BASE), &MsrRegister, StdHeader);
((POPUP_PSTATE_REGISTER *) &OrMask)->PopupCpuVid = (UINT32) ((PSTATE_MSR *) &MsrRegister)->CpuVid;
((POPUP_PSTATE_REGISTER *) &OrMask)->PopupCpuFid = (UINT32) ((PSTATE_MSR *) &MsrRegister)->CpuFid;
((POPUP_PSTATE_REGISTER *) &OrMask)->PopupCpuDid = (UINT32) ((PSTATE_MSR *) &MsrRegister)->CpuDid;
LibAmdMsrRead ((((CLK_PWR_TIMING_CTRL2_REGISTER *) &PciRegister)->PstateMaxVal + PS_REG_BASE), &MsrReg, StdHeader);
((POPUP_PSTATE_REGISTER *) &OrMask)->PopupCpuVid = (UINT32) ((PSTATE_MSR *) &MsrReg)->CpuVid;
((POPUP_PSTATE_REGISTER *) &OrMask)->PopupCpuFid = (UINT32) ((PSTATE_MSR *) &MsrReg)->CpuFid;
((POPUP_PSTATE_REGISTER *) &OrMask)->PopupCpuDid = (UINT32) ((PSTATE_MSR *) &MsrReg)->CpuDid;
PciAddress.Address.Register = POPUP_PSTATE_REG;
ModifyCurrentSocketPci (&PciAddress, AndMask, OrMask, StdHeader);
@ -278,7 +278,7 @@ F10CpuAmdPmPwrPlaneInit (
AndMask = 0xFFFFFFFF;
((CLK_PWR_TIMING_CTRL1_REGISTER *) &AndMask)->AltVidStart = 0;
OrMask = 0x00000000;
((CLK_PWR_TIMING_CTRL1_REGISTER *) &OrMask)->AltVidStart = (UINT32) ((PSTATE_MSR *) &MsrRegister)->CpuVid;
((CLK_PWR_TIMING_CTRL1_REGISTER *) &OrMask)->AltVidStart = (UINT32) ((PSTATE_MSR *) &MsrReg)->CpuVid;
ModifyCurrentSocketPci (&PciAddress, AndMask, OrMask, StdHeader);
// Set up Altvid slam time
@ -323,20 +323,20 @@ F10PmPwrPlaneInitPviCore (
UINT32 MsrAddr;
UINT32 NbVid;
UINT32 CpuVid;
UINT64 MsrRegister;
UINT64 MsrReg;
for (MsrAddr = PS_REG_BASE; MsrAddr <= PS_MAX_REG; MsrAddr++) {
LibAmdMsrRead (MsrAddr, &MsrRegister, StdHeader);
if (((PSTATE_MSR *) &MsrRegister)->PsEnable == (UINT64) 1) {
NbVid = (UINT32) (((PSTATE_MSR *) &MsrRegister)->NbVid);
CpuVid = (UINT32) (((PSTATE_MSR *) &MsrRegister)->CpuVid);
LibAmdMsrRead (MsrAddr, &MsrReg, StdHeader);
if (((PSTATE_MSR *) &MsrReg)->PsEnable == (UINT64) 1) {
NbVid = (UINT32) (((PSTATE_MSR *) &MsrReg)->NbVid);
CpuVid = (UINT32) (((PSTATE_MSR *) &MsrReg)->CpuVid);
if (NbVid != CpuVid) {
if (NbVid > CpuVid) {
NbVid = CpuVid;
}
((PSTATE_MSR *) &MsrRegister)->NbVid = NbVid;
((PSTATE_MSR *) &MsrRegister)->CpuVid = NbVid;
LibAmdMsrWrite (MsrAddr, &MsrRegister, StdHeader);
((PSTATE_MSR *) &MsrReg)->NbVid = NbVid;
((PSTATE_MSR *) &MsrReg)->CpuVid = NbVid;
LibAmdMsrWrite (MsrAddr, &MsrReg, StdHeader);
}
}
}
@ -375,7 +375,7 @@ F10CalculateAltvidVSSlamTimeOnCore (
UINT8 PminVidCode;
UINT32 MsrAddr;
UINT32 PciRegister;
UINT64 MsrRegister;
UINT64 MsrReg;
PCI_ADDR LocalPciAddress;
// Calculate Slam Time
@ -384,17 +384,17 @@ F10CalculateAltvidVSSlamTimeOnCore (
// decimals.
// Get Pmin's index
LibAmdMsrRead (MSR_PSTATE_CURRENT_LIMIT, &MsrRegister, StdHeader);
MsrAddr = (UINT32) ((((PSTATE_CURLIM_MSR *) &MsrRegister)->PstateMaxVal) + PS_REG_BASE);
LibAmdMsrRead (MSR_PSTATE_CURRENT_LIMIT, &MsrReg, StdHeader);
MsrAddr = (UINT32) ((((PSTATE_CURLIM_MSR *) &MsrReg)->PstateMaxVal) + PS_REG_BASE);
// Get Pmin's VID
LibAmdMsrRead (MsrAddr, &MsrRegister, StdHeader);
PminVidCode = (UINT8) (((PSTATE_MSR *) &MsrRegister)->CpuVid);
LibAmdMsrRead (MsrAddr, &MsrReg, StdHeader);
PminVidCode = (UINT8) (((PSTATE_MSR *) &MsrReg)->CpuVid);
// If SVI, we only care about CPU VID.
// If PVI, determine the higher voltage b/t NB and CPU
if (PviModeFlag) {
NbVid = (UINT8) (((PSTATE_MSR *) &MsrRegister)->NbVid);
NbVid = (UINT8) (((PSTATE_MSR *) &MsrReg)->NbVid);
if (PminVidCode > NbVid) {
PminVidCode = NbVid;
}

34
src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10Pstate.c
View File

@ -308,13 +308,13 @@ F10GetPstateFrequency (
UINT8 TempValue;
UINT32 CpuDid;
UINT32 CpuFid;
UINT64 MsrRegister;
UINT64 MsrReg;
ASSERT (StateNumber < NM_PS_REG);
LibAmdMsrRead (PS_REG_BASE + (UINT32) StateNumber, &MsrRegister, StdHeader);
ASSERT (((PSTATE_MSR *) &MsrRegister)->PsEnable == 1);
CpuDid = (UINT32) (((PSTATE_MSR *) &MsrRegister)->CpuDid);
CpuFid = (UINT32) (((PSTATE_MSR *) &MsrRegister)->CpuFid);
LibAmdMsrRead (PS_REG_BASE + (UINT32) StateNumber, &MsrReg, StdHeader);
ASSERT (((PSTATE_MSR *) &MsrReg)->PsEnable == 1);
CpuDid = (UINT32) (((PSTATE_MSR *) &MsrReg)->CpuDid);
CpuFid = (UINT32) (((PSTATE_MSR *) &MsrReg)->CpuFid);
switch (CpuDid) {
case 0:
@ -380,7 +380,7 @@ F10PstateLevelingCoreMsrModify (
PCI_ADDR PciAddress;
CPU_SPECIFIC_SERVICES *FamilySpecificServices;
GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader);
GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
ASSERT (FamilySpecificServices != NULL);
Ignored = 0;
@ -521,15 +521,15 @@ F10GetPstatePower (
UINT32 Power;
PCI_ADDR PciAddress;
UINT32 TempVar_a;
UINT64 MsrRegister;
UINT64 MsrReg;
AGESA_STATUS IgnoredSts;
ASSERT (StateNumber < NM_PS_REG);
LibAmdMsrRead (PS_REG_BASE + (UINT32) StateNumber, &MsrRegister, StdHeader);
ASSERT (((PSTATE_MSR *) &MsrRegister)->PsEnable == 1);
CpuVid = (UINT32) (((PSTATE_MSR *) &MsrRegister)->CpuVid);
IddValue = (UINT32) (((PSTATE_MSR *) &MsrRegister)->IddValue);
IddDiv = (UINT32) (((PSTATE_MSR *) &MsrRegister)->IddDiv);
LibAmdMsrRead (PS_REG_BASE + (UINT32) StateNumber, &MsrReg, StdHeader);
ASSERT (((PSTATE_MSR *) &MsrReg)->PsEnable == 1);
CpuVid = (UINT32) (((PSTATE_MSR *) &MsrReg)->CpuVid);
IddValue = (UINT32) (((PSTATE_MSR *) &MsrReg)->IddValue);
IddDiv = (UINT32) (((PSTATE_MSR *) &MsrReg)->IddDiv);
IdentifyCore (StdHeader, &Socket, &Module, &Ignored, &IgnoredSts);
GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredSts);
@ -654,7 +654,7 @@ F10GetPstateRegisterInfo (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT64 MsrRegister;
UINT64 MsrReg;
UINT32 PciRegister;
PCI_ADDR PciAddress;
CPUID_DATA CpuidData;
@ -672,9 +672,9 @@ F10GetPstateRegisterInfo (
*SwPstateNumber = PState;
// Read PSTATE MSRs
LibAmdMsrRead (PS_REG_BASE + (UINT32) PState, &MsrRegister, StdHeader);
LibAmdMsrRead (PS_REG_BASE + (UINT32) PState, &MsrReg, StdHeader);
if (((PSTATE_MSR *) &MsrRegister)->PsEnable == 1) {
if (((PSTATE_MSR *) &MsrReg)->PsEnable == 1) {
// PState enable = bit 63
*PStateEnabled = TRUE;
// Check input pstate belongs to Boosted-Pstate, if yes, return *PStateEnabled = FALSE.
@ -688,9 +688,9 @@ F10GetPstateRegisterInfo (
}
// Bits 39:32 (high 32 bits [7:0])
*IddVal = (UINT32) ((PSTATE_MSR *) &MsrRegister)->IddValue;
*IddVal = (UINT32) ((PSTATE_MSR *) &MsrReg)->IddValue;
// Bits 41:40 (high 32 bits [9:8])
*IddDiv = (UINT32) ((PSTATE_MSR *) &MsrRegister)->IddDiv;
*IddDiv = (UINT32) ((PSTATE_MSR *) &MsrReg)->IddDiv;
return (AGESA_SUCCESS);
}

76
src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10Utilities.c
View File

@ -119,7 +119,7 @@ F10PmSwVoltageTransition (
UINT32 Socket;
UINT32 Module;
UINT32 Ignored;
UINT64 MsrRegister;
UINT64 MsrReg;
PCI_ADDR PciAddress;
AGESA_STATUS IgnoredSts;
@ -130,9 +130,9 @@ F10PmSwVoltageTransition (
PciAddress.Address.Register = PW_CTL_MISC_REG;
LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
if (((POWER_CTRL_MISC_REGISTER *) &PciRegister)->SlamVidMode == 1) {
LibAmdMsrRead (MSR_COFVID_CTL, &MsrRegister, StdHeader);
((COFVID_CTRL_MSR *) &MsrRegister)->CpuVid = VidCode;
LibAmdMsrWrite (MSR_COFVID_CTL, &MsrRegister, StdHeader);
LibAmdMsrRead (MSR_COFVID_CTL, &MsrReg, StdHeader);
((COFVID_CTRL_MSR *) &MsrReg)->CpuVid = VidCode;
LibAmdMsrWrite (MSR_COFVID_CTL, &MsrReg, StdHeader);
F10WaitOutVoltageTransition (TRUE, StdHeader);
} else
return;
@ -270,22 +270,22 @@ F10SwVoltageTransitionServerNbCore (
)
{
UINT32 VidCode;
UINT64 MsrRegister;
UINT64 MsrReg;
if (((SW_VOLT_TRANS_NB *) InputData)->SlamMode) {
VidCode = ((SW_VOLT_TRANS_NB *) InputData)->VidCode;
} else {
LibAmdMsrRead (MSR_COFVID_STS, &MsrRegister, StdHeader);
VidCode = (UINT32) (((COFVID_STS_MSR *) &MsrRegister)->CurNbVid);
LibAmdMsrRead (MSR_COFVID_STS, &MsrReg, StdHeader);
VidCode = (UINT32) (((COFVID_STS_MSR *) &MsrReg)->CurNbVid);
if (VidCode > ((SW_VOLT_TRANS_NB *) InputData)->VidCode) {
--VidCode;
} else if (VidCode < ((SW_VOLT_TRANS_NB *) InputData)->VidCode) {
++VidCode;
}
}
LibAmdMsrRead (MSR_COFVID_CTL, &MsrRegister, StdHeader);
((COFVID_CTRL_MSR *) &MsrRegister)->NbVid = VidCode;
LibAmdMsrWrite (MSR_COFVID_CTL, &MsrRegister, StdHeader);
LibAmdMsrRead (MSR_COFVID_CTL, &MsrReg, StdHeader);
((COFVID_CTRL_MSR *) &MsrReg)->NbVid = VidCode;
LibAmdMsrWrite (MSR_COFVID_CTL, &MsrReg, StdHeader);
if (VidCode == ((SW_VOLT_TRANS_NB *) InputData)->VidCode) {
return 0;
@ -323,7 +323,7 @@ F10ProgramVSSlamTimeOnSocket (
UINT32 MsrAddr;
UINT32 OrMask;
UINT32 PciRegister;
UINT64 MsrRegister;
UINT64 MsrReg;
BOOLEAN IsPviMode;
PCI_ADDR LocalPciAddress;
@ -339,30 +339,30 @@ F10ProgramVSSlamTimeOnSocket (
}
// Get P0's voltage
LibAmdMsrRead (PS_REG_BASE, &MsrRegister, StdHeader);
P0VidCode = (UINT8) (((PSTATE_MSR *) &MsrRegister)->CpuVid);
LibAmdMsrRead (PS_REG_BASE, &MsrReg, StdHeader);
P0VidCode = (UINT8) (((PSTATE_MSR *) &MsrReg)->CpuVid);
// If SVI, we only care about CPU VID.
// If PVI, determine the higher voltage between NB and CPU
if (IsPviMode) {
NbVid = (UINT8) (((PSTATE_MSR *) &MsrRegister)->NbVid);
NbVid = (UINT8) (((PSTATE_MSR *) &MsrReg)->NbVid);
if (P0VidCode > NbVid) {
P0VidCode = NbVid;
}
}
// Get Pmin's index
LibAmdMsrRead (MSR_PSTATE_CURRENT_LIMIT, &MsrRegister, StdHeader);
MsrAddr = (UINT32) ((((PSTATE_CURLIM_MSR *) &MsrRegister)->PstateMaxVal) + PS_REG_BASE);
LibAmdMsrRead (MSR_PSTATE_CURRENT_LIMIT, &MsrReg, StdHeader);
MsrAddr = (UINT32) ((((PSTATE_CURLIM_MSR *) &MsrReg)->PstateMaxVal) + PS_REG_BASE);
// Get Pmin's VID
LibAmdMsrRead (MsrAddr, &MsrRegister, StdHeader);
PminVidCode = (UINT8) (((PSTATE_MSR *) &MsrRegister)->CpuVid);
LibAmdMsrRead (MsrAddr, &MsrReg, StdHeader);
PminVidCode = (UINT8) (((PSTATE_MSR *) &MsrReg)->CpuVid);
// If SVI, we only care about CPU VID.
// If PVI, determine the higher voltage b/t NB and CPU
if (IsPviMode) {
NbVid = (UINT8) (((PSTATE_MSR *) &MsrRegister)->NbVid);
NbVid = (UINT8) (((PSTATE_MSR *) &MsrReg)->NbVid);
if (PminVidCode > NbVid) {
PminVidCode = NbVid;
}
@ -459,12 +459,12 @@ F10DisablePstate (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT64 MsrRegister;
UINT64 MsrReg;
ASSERT (StateNumber < NM_PS_REG);
LibAmdMsrRead (PS_REG_BASE + (UINT32) StateNumber, &MsrRegister, StdHeader);
((PSTATE_MSR *) &MsrRegister)->PsEnable = 0;
LibAmdMsrWrite (PS_REG_BASE + (UINT32) StateNumber, &MsrRegister, StdHeader);
LibAmdMsrRead (PS_REG_BASE + (UINT32) StateNumber, &MsrReg, StdHeader);
((PSTATE_MSR *) &MsrReg)->PsEnable = 0;
LibAmdMsrWrite (PS_REG_BASE + (UINT32) StateNumber, &MsrReg, StdHeader);
return (AGESA_SUCCESS);
}
@ -489,18 +489,18 @@ F10TransitionPstate (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT64 MsrRegister;
UINT64 MsrReg;
ASSERT (StateNumber < NM_PS_REG);
LibAmdMsrRead (PS_REG_BASE + (UINT32) StateNumber, &MsrRegister, StdHeader);
ASSERT (((PSTATE_MSR *) &MsrRegister)->PsEnable == 1);
LibAmdMsrRead (MSR_PSTATE_CTL, &MsrRegister, StdHeader);
((PSTATE_CTRL_MSR *) &MsrRegister)->PstateCmd = (UINT64) StateNumber;
LibAmdMsrWrite (MSR_PSTATE_CTL, &MsrRegister, StdHeader);
LibAmdMsrRead (PS_REG_BASE + (UINT32) StateNumber, &MsrReg, StdHeader);
ASSERT (((PSTATE_MSR *) &MsrReg)->PsEnable == 1);
LibAmdMsrRead (MSR_PSTATE_CTL, &MsrReg, StdHeader);
((PSTATE_CTRL_MSR *) &MsrReg)->PstateCmd = (UINT64) StateNumber;
LibAmdMsrWrite (MSR_PSTATE_CTL, &MsrReg, StdHeader);
if (WaitForTransition) {
do {
LibAmdMsrRead (MSR_PSTATE_STS, &MsrRegister, StdHeader);
} while (((PSTATE_STS_MSR *) &MsrRegister)->CurPstate != (UINT64) StateNumber);
LibAmdMsrRead (MSR_PSTATE_STS, &MsrReg, StdHeader);
} while (((PSTATE_STS_MSR *) &MsrReg)->CurPstate != (UINT64) StateNumber);
}
return (AGESA_SUCCESS);
}
@ -525,15 +525,15 @@ F10GetTscRate (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT64 MsrRegister;
UINT64 MsrReg;
PSTATE_CPU_FAMILY_SERVICES *FamilyServices;
FamilyServices = NULL;
GetFeatureServicesOfCurrentCore (&PstateFamilyServiceTable, &FamilyServices, StdHeader);
GetFeatureServicesOfCurrentCore (&PstateFamilyServiceTable, (const VOID **)&FamilyServices, StdHeader);
ASSERT (FamilyServices != NULL);
LibAmdMsrRead (0xC0010015, &MsrRegister, StdHeader);
if ((MsrRegister & 0x01000000) != 0) {
LibAmdMsrRead (0xC0010015, &MsrReg, StdHeader);
if ((MsrReg & 0x01000000) != 0) {
return (FamilyServices->GetPstateFrequency (FamilyServices, 0, FrequencyInMHz, StdHeader));
} else {
return (FamilySpecificServices->GetCurrentNbFrequency (FamilySpecificServices, FrequencyInMHz, StdHeader));
@ -564,7 +564,7 @@ F10GetCurrentNbFrequency (
UINT32 Core;
UINT32 NbFid;
UINT32 PciRegister;
UINT64 MsrRegister;
UINT64 MsrReg;
PCI_ADDR PciAddress;
AGESA_STATUS ReturnCode;
@ -577,8 +577,8 @@ F10GetCurrentNbFrequency (
PciAddress.Address.Register = CPTC0_REG;
LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
NbFid = ((CLK_PWR_TIMING_CTRL_REGISTER *) &PciRegister)->NbFid;
LibAmdMsrRead (MSR_COFVID_STS, &MsrRegister, StdHeader);
if (((COFVID_STS_MSR *) &MsrRegister)->CurNbDid == 0) {
LibAmdMsrRead (MSR_COFVID_STS, &MsrReg, StdHeader);
if (((COFVID_STS_MSR *) &MsrReg)->CurNbDid == 0) {
*FrequencyInMHz = ((NbFid + 4) * 200);
} else {
*FrequencyInMHz = (((NbFid + 4) * 200) / 2);

6
src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/F14C6State.c
View File

@ -144,12 +144,12 @@ F14InitializeC6 (
UINT32 i;
UINT32 MaxEnabledPstate;
UINT32 PciRegister;
UINT64 MsrRegister;
UINT64 MsrReg;
PCI_ADDR PciAddress;
for (i = MSR_PSTATE_7; i > MSR_PSTATE_0; i--) {
LibAmdMsrRead (i, &MsrRegister, StdHeader);
if (((PSTATE_MSR *) &MsrRegister)->PsEnable == 1) {
LibAmdMsrRead (i, &MsrReg, StdHeader);
if (((PSTATE_MSR *) &MsrReg)->PsEnable == 1) {
break;
}
}

16
src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/F14IoCstate.c
View File

@ -115,28 +115,28 @@ F14InitializeIoCstate (
UINT32 i;
UINT32 MaxEnabledPstate;
UINT32 PciRegister;
UINT64 MsrRegister;
UINT64 MsrReg;
AP_TASK TaskPtr;
PCI_ADDR PciAddress;
if ((EntryPoint & CPU_FEAT_AFTER_PM_INIT) != 0) {
for (i = MSR_PSTATE_7; i > MSR_PSTATE_0; i--) {
LibAmdMsrRead (i, &MsrRegister, StdHeader);
if (((PSTATE_MSR *) &MsrRegister)->PsEnable == 1) {
LibAmdMsrRead (i, &MsrReg, StdHeader);
if (((PSTATE_MSR *) &MsrReg)->PsEnable == 1) {
break;
}
}
MaxEnabledPstate = i - MSR_PSTATE_0;
// Initialize MSRC001_0073[CstateAddr] on each core to a region of
// the IO address map with 8 consecutive available addresses.
MsrRegister = 0;
((CSTATE_ADDRESS_MSR *) &MsrRegister)->CstateAddr = PlatformConfig->CStateIoBaseAddress;
ASSERT ((((CSTATE_ADDRESS_MSR *) &MsrRegister)->CstateAddr != 0) &&
(((CSTATE_ADDRESS_MSR *) &MsrRegister)->CstateAddr <= 0xFFF8));
MsrReg = 0;
((CSTATE_ADDRESS_MSR *) &MsrReg)->CstateAddr = PlatformConfig->CStateIoBaseAddress;
ASSERT ((((CSTATE_ADDRESS_MSR *) &MsrReg)->CstateAddr != 0) &&
(((CSTATE_ADDRESS_MSR *) &MsrReg)->CstateAddr <= 0xFFF8));
TaskPtr.FuncAddress.PfApTaskI = F14InitializeIoCstateOnCore;
TaskPtr.DataTransfer.DataSizeInDwords = 2;
TaskPtr.DataTransfer.DataPtr = &MsrRegister;
TaskPtr.DataTransfer.DataPtr = &MsrReg;
TaskPtr.DataTransfer.DataTransferFlags = 0;
TaskPtr.ExeFlags = WAIT_FOR_CORE;
ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, NULL);

4
src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/F14MicrocodePatch0500000B.c
View File

@ -63,7 +63,7 @@
// Patch code 0500000B for 5000 and equivalent
CONST MICROCODE_PATCHES ROMDATA CpuF14MicrocodePatch0500000B =
{
{{
0x10,
0x20,
0x01,
@ -1632,7 +1632,7 @@ CONST MICROCODE_PATCHES ROMDATA CpuF14MicrocodePatch0500000B =
0xe9,
0xb2,
0x6d
};
}};
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S

4
src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/F14MicrocodePatch0500001A.c
View File

@ -63,7 +63,7 @@
// Patch code 0500001A for 5001 and equivalent
CONST MICROCODE_PATCHES ROMDATA CpuF14MicrocodePatch0500001A =
{
{{
0x10,
0x20,
0x08,
@ -1632,7 +1632,7 @@ CONST MICROCODE_PATCHES ROMDATA CpuF14MicrocodePatch0500001A =
0x73,
0x52,
0x3b
};
}};
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S

1900
src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/F14MicrocodePatch05000028.c Normal file
View File

File diff suppressed because it is too large Load Diff

1645
src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/F14MicrocodePatch05000101.c Normal file
View File

File diff suppressed because it is too large Load Diff

187
src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/ON/F14OnCpb.c Normal file
View File

@ -0,0 +1,187 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD Family 14 Ontario CPB Initialization
*
* Enables core performance boost.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/Family/0x14/ON
* @e \$Revision: 46389 $ @e \$Date: 2011-01-31 22:22:49 -0500 (Mon, 31 Jan 2011) $
*
*/
/*
******************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "amdlib.h"
#include "cpuFamilyTranslation.h"
#include "cpuF14PowerMgmt.h"
#include "GnbRegistersON.h"
#include "NbSmuLib.h"
#include "NbSmuLib.h"
#include "cpuFeatures.h"
#include "cpuCpb.h"
#include "Filecode.h"
CODE_GROUP (G1_PEICC)
RDATA_GROUP (G1_PEICC)
#define FILECODE PROC_CPU_FAMILY_0X14_ON_F14ONCPB_FILECODE
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------*/
/**
* BSC entry point for checking whether or not CPB is supported.
*
* @param[in] CpbServices The current CPU's family services.
* @param[in] PlatformConfig Contains the runtime modifiable feature input data.
* @param[in] Socket Zero based socket number to check.
* @param[in] StdHeader Config handle for library and services.
*
* @retval TRUE CPB is supported.
* @retval FALSE CPB is not supported.
*
*/
BOOLEAN
STATIC
F14OnIsCpbSupported (
IN CPB_FAMILY_SERVICES *CpbServices,
IN PLATFORM_CONFIGURATION *PlatformConfig,
IN UINT32 Socket,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
PCI_ADDR PciAddress;
CPB_CTRL_REGISTER CpbControl;
CPU_LOGICAL_ID CpuFamilyRevision;
GetLogicalIdOfCurrentCore (&CpuFamilyRevision, StdHeader);
if ((CpuFamilyRevision.Revision & (AMD_F14_ON_Ax | AMD_F14_ON_Bx)) != 0) {
return FALSE;
} else {
PciAddress.AddressValue = CPB_CTRL_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &CpbControl, StdHeader);
return (BOOLEAN) (CpbControl.NumBoostStates != 0);
}
}
/*---------------------------------------------------------------------------------------*/
/**
* BSC entry point for enabling Core Performance Boost.
*
* Set up D18F4x15C[BoostSrc] and start the PDMs according to the BKDG.
*
* @param[in] CpbServices The current CPU's family services.
* @param[in] PlatformConfig Contains the runtime modifiable feature input data.
* @param[in] EntryPoint Current CPU feature dispatch point.
* @param[in] Socket Zero based socket number to check.
* @param[in] StdHeader Config handle for library and services.
*
* @retval AGESA_SUCCESS Always succeeds.
*
*/
AGESA_STATUS
STATIC
F14OnInitializeCpb (
IN CPB_FAMILY_SERVICES *CpbServices,
IN PLATFORM_CONFIGURATION *PlatformConfig,
IN UINT64 EntryPoint,
IN UINT32 Socket,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
PCI_ADDR PciAddress;
CPB_CTRL_REGISTER CpbControl;
LPMV_SCALAR2_REGISTER LpmvScalar2;
SMUx0B_x8580_STRUCT SMUx0Bx8580;
if ((EntryPoint & CPU_FEAT_BEFORE_PM_INIT) != 0) {
// F4x14C [25:24] ApmCstExtPol = 1
PciAddress.AddressValue = LPMV_SCALAR2_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &LpmvScalar2, StdHeader);
LpmvScalar2.ApmCstExtPol = 1;
LibAmdPciWrite (AccessWidth32, PciAddress, &LpmvScalar2, StdHeader);
// F4x15C [1:0] BoostSrc = 1
// F4x15C [29] BoostEnAllCores = 1
PciAddress.AddressValue = CPB_CTRL_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &CpbControl, StdHeader);
CpbControl.BoostSrc = 1;
CpbControl.BoostEnAllCores = 1;
IDS_OPTION_HOOK (IDS_CPB_CTRL, &CpbControl, StdHeader);
LibAmdPciWrite (AccessWidth32, PciAddress, &CpbControl, StdHeader);
} else if ((EntryPoint & CPU_FEAT_INIT_LATE_END) != 0) {
// Ensure that the recommended settings have been programmed into SMUx0B_x8580, then
// interrupt the SMU with service index 12h.
NbSmuRcuRegisterRead (SMUx0B_x8580_ADDRESS, &SMUx0Bx8580.Value, 1, StdHeader);
SMUx0Bx8580.Field.PdmPeriod = 0x1388;
SMUx0Bx8580.Field.PdmParamLoc = 0;
SMUx0Bx8580.Field.PdmCacEn = 1;
SMUx0Bx8580.Field.PdmUnit = 1;
SMUx0Bx8580.Field.PdmEn = 1;
NbSmuRcuRegisterWrite (SMUx0B_x8580_ADDRESS, &SMUx0Bx8580.Value, 1, TRUE, StdHeader);
NbSmuServiceRequest (0x12, TRUE, StdHeader);
}
return AGESA_SUCCESS;
}
CONST CPB_FAMILY_SERVICES ROMDATA F14OnCpbSupport =
{
0,
F14OnIsCpbSupported,
F14OnInitializeCpb
};

16
src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/ON/F14OnEquivalenceTable.c
View File

@ -7,7 +7,7 @@
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/Family/0x14
* @e \$Revision: 36418 $ @e \$Date: 2010-08-18 17:00:58 +0800 (Wed, 18 Aug 2010) $
* @e \$Revision: 48589 $ @e \$Date: 2011-03-10 09:27:00 -0700 (Thu, 10 Mar 2011) $
*
*/
/*
@ -68,6 +68,14 @@
*----------------------------------------------------------------------------------------
*/
VOID
GetF14OnMicrocodeEquivalenceTable (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
OUT CONST VOID **OnEquivalenceTablePtr,
OUT UINT8 *NumberOfElements,
IN AMD_CONFIG_PARAMS *StdHeader
);
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
@ -77,7 +85,8 @@ STATIC CONST UINT16 ROMDATA CpuF14MicrocodeEquivalenceTable[] =
{
0x5000, 0x5000,
0x5001, 0x5001,
0x5010, 0x5010
0x5010, 0x5010,
0x5020, 0x5020
};
// Unencrypted equivalent
@ -85,7 +94,8 @@ STATIC CONST UINT16 ROMDATA CpuF14UnEncryptedMicrocodeEquivalenceTable[] =
{
0x5000, 0x5800,
0x5001, 0x5801,
0x5010, 0x5810
0x5010, 0x5810,
0x5020, 0x5820
};

10
src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/ON/F14OnInitEarlyTable.c
View File

@ -87,6 +87,14 @@ extern F14_ES_CORE_SUPPORT F14EarlySampleCoreSupport;
*----------------------------------------------------------------------------------------
*/
VOID
GetF14OnEarlyInitOnCoreTable (
IN CPU_SPECIFIC_SERVICES *FamilyServices,
OUT CONST S_PERFORM_EARLY_INIT_ON_CORE **Table,
IN AMD_CPU_EARLY_PARAMS *EarlyParams,
IN AMD_CONFIG_PARAMS *StdHeader
);
VOID
F14OnLoadMicrocodePatchAtEarly (
IN CPU_SPECIFIC_SERVICES *FamilyServices,
IN AMD_CPU_EARLY_PARAMS *EarlyParams,
@ -144,7 +152,7 @@ GetF14OnEarlyInitOnCoreTable (
{
*Table = F14OnEarlyInitOnCoreTable;
F14EarlySampleCoreSupport.F14GetEarlyInitTableHook (Table, StdHeader);
F14EarlySampleCoreSupport.F14GetEarlyInitTableHook ((const VOID **)Table, StdHeader);
}
/*---------------------------------------------------------------------------------------*/

12
src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/ON/F14OnLogicalIdTables.c
View File

@ -66,6 +66,14 @@
*----------------------------------------------------------------------------------------
*/
VOID
GetF14OnLogicalIdAndRev (
OUT CONST CPU_LOGICAL_ID_XLAT **OnIdPtr,
OUT UINT8 *NumberOfElements,
OUT UINT64 *LogicalFamily,
IN OUT AMD_CONFIG_PARAMS *StdHeader
);
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
@ -84,6 +92,10 @@ STATIC CONST CPU_LOGICAL_ID_XLAT ROMDATA CpuF14OnLogicalIdAndRevArray[] =
{
0x5010,
AMD_F14_ON_B0
},
{
0x5020,
AMD_F14_ON_C0
}
};

8
src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/ON/F14OnMicrocodePatchTables.c
View File

@ -70,6 +70,14 @@ extern CONST UINT8 ROMDATA CpuF14OnNumberOfMicrocodePatches;
*----------------------------------------------------------------------------------------
*/
VOID
GetF14OnMicroCodePatchesStruct (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
OUT CONST VOID **OnUcodePtr,
OUT UINT8 *NumberOfElements,
IN AMD_CONFIG_PARAMS *StdHeader
);
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------

105
src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/ON/F14OnPciTables.c Normal file
View File

@ -0,0 +1,105 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD Family_14 Ontario PCI tables with values as defined in BKDG
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/FAMILY/0x14/ON
* @e \$Revision: 46389 $ @e \$Date: 2011-01-31 22:22:49 -0500 (Mon, 31 Jan 2011) $
*
*/
/*
******************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "cpuRegisters.h"
#include "Table.h"
#include "Filecode.h"
#define FILECODE PROC_CPU_FAMILY_0X14_ON_F14ONPCITABLES_FILECODE
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
// P C I T a b l e s
// ----------------------
STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F14OnPciRegisters[] =
{
// Function 4
// D18F4x104 - TDP Lock Accumulator
// bits[1:0] TdpLockDivVal = 1
// bits[13:2] TdpLockDivRate = 0x190
// bits[16:15] TdpLockDivValCpu = 1
// bits[28:17] TdpLockDivRateCpu = 0x190
{
PciRegister,
{
AMD_FAMILY_14, // CpuFamily
AMD_F14_ON_Cx // CpuRevision
},
{AMD_PF_ALL}, // platformFeatures
{{
MAKE_SBDFO (0, 0, 24, FUNC_4, 0x104), // Address
0x03208641, // regData
0x1FFFBFFF, // regMask
}}
},
};
CONST REGISTER_TABLE ROMDATA F14OnPciRegisterTable = {
PrimaryCores,
(sizeof (F14OnPciRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
F14OnPciRegisters,
};

43
src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuCommonF14Utilities.c
View File

@ -112,6 +112,18 @@ CONST UINT16 ROMDATA F14MaxNbFreqAtMinVidFreqTable[] =
*----------------------------------------------------------------------------------------
*/
UINT32
F14GetApCoreNumber (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN AMD_CONFIG_PARAMS *StdHeader
);
CORE_ID_POSITION
F14CpuAmdCoreIdPositionInInitialApicId (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN AMD_CONFIG_PARAMS *StdHeader
);
UINT32
STATIC
RoundedDivision (
IN UINT32 Dividend,
@ -300,6 +312,7 @@ F14NbPstateInit (
UINT32 TargetNumerator;
UINT32 TargetDenominator;
BOOLEAN ReturnStatus;
BOOLEAN WaitForTransition;
PCI_ADDR PciAddress;
D18F3xD4_STRUCT Cptc0;
D18F3xDC_STRUCT Cptc2;
@ -313,6 +326,7 @@ F14NbPstateInit (
// F14 only supports NB P0 and NB P1
ASSERT (TargetNbPstate < 2);
WaitForTransition = FALSE;
ReturnStatus = TRUE;
// Get D18F3xD4[MainPllOpFreqId] frequency
@ -383,8 +397,11 @@ F14NbPstateInit (
// Apply the appropriate P0 frequency
PciAddress.AddressValue = CPTC2_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &Cptc2.Value, StdHeader);
if (Cptc2.Field.NbPs0NclkDiv != EncodedNbPs0NclkDiv) {
WaitForTransition = TRUE;
Cptc2.Field.NbPs0NclkDiv = EncodedNbPs0NclkDiv;
LibAmdPciWrite (AccessWidth32, PciAddress, &Cptc2.Value, StdHeader);
}
NbP0Cof = RoundedDivision (NbPstateNumerator, EncodedNbPs0NclkDiv);
// Determine NB P1 settings if necessary
@ -434,6 +451,13 @@ F14NbPstateInit (
NbP1Cof = 0;
}
*CurrentNbFreq = NbP0Cof;
if (WaitForTransition) {
// Ensure that the frequency has settled before returning to memory code.
PciAddress.AddressValue = CPTC2_PCI_ADDR;
do {
LibAmdPciRead (AccessWidth32, PciAddress, &Cptc2.Value, StdHeader);
} while (Cptc2.Field.NclkFreqDone != 1);
}
} else {
// Get NB P0 COF
PciAddress.AddressValue = CPTC2_PCI_ADDR;
@ -457,12 +481,7 @@ F14NbPstateInit (
NbPsCfgLow.Field.NbPsForceSel = 1;
LibAmdPciWrite (AccessWidth32, PciAddress, &NbPsCfgLow.Value, StdHeader);
// Wait for the transition to complete.
PciAddress.AddressValue = NB_PSTATE_CTRL_STS_PCI_ADDR;
do {
LibAmdPciRead (AccessWidth32, PciAddress, &NbPsCtrlSts.Value, StdHeader);
} while (NbPsCtrlSts.Field.NbPs1Act != 1);
WaitForTransition = TRUE;
*CurrentNbFreq = RoundedDivision (NbPstateNumerator, NbPsCfgLow.Field.NbPs1NclkDiv);
} else {
// No NB P-states. Return FALSE, and set current frequency to P0.
@ -476,15 +495,17 @@ F14NbPstateInit (
// Request transition to P0
NbPsCfgLow.Field.NbPsForceSel = 0;
LibAmdPciWrite (AccessWidth32, PciAddress, &NbPsCfgLow.Value, StdHeader);
WaitForTransition = TRUE;
}
}
}
if (WaitForTransition) {
// Ensure that the frequency has settled before returning to memory code.
PciAddress.AddressValue = CPTC2_PCI_ADDR;
PciAddress.AddressValue = NB_PSTATE_CTRL_STS_PCI_ADDR;
do {
LibAmdPciRead (AccessWidth32, PciAddress, &Cptc2.Value, StdHeader);
} while (Cptc2.Field.NclkFreqDone != 1);
LibAmdPciRead (AccessWidth32, PciAddress, &NbPsCtrlSts.Value, StdHeader);
} while (NbPsCtrlSts.Field.NbPs1Act != TargetNbPstate);
}
}
return ReturnStatus;
}

16
src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14BrandId.c
View File

@ -70,6 +70,22 @@
*----------------------------------------------------------------------------------------
*/
VOID
GetF14BrandIdString1 (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
OUT CONST VOID **BrandString1Ptr,
OUT UINT8 *NumberOfElements,
IN AMD_CONFIG_PARAMS *StdHeader
);
VOID
GetF14BrandIdString2 (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
OUT CONST VOID **BrandString2Ptr,
OUT UINT8 *NumberOfElements,
IN AMD_CONFIG_PARAMS *StdHeader
);
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------

18
src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14BrandIdFt1.c
View File

@ -9,7 +9,7 @@
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU
* @e \$Revision: 40034 $ @e \$Date: 2010-10-19 04:03:22 +0800 (Tue, 19 Oct 2010) $
* @e \$Revision: 45203 $ @e \$Date: 2011-01-13 12:36:39 -0700 (Thu, 13 Jan 2011) $
*
*/
/*
@ -77,6 +77,7 @@
CONST CHAR8 ROMDATA str_AMD_C[] = "AMD C-";
CONST CHAR8 ROMDATA str_AMD_E[] = "AMD E-";
CONST CHAR8 ROMDATA str_AMD_G_T[] = "AMD G-T";
CONST CHAR8 ROMDATA str_AMD_Z[] = "AMD Z-";
// String2
CONST CHAR8 ROMDATA str___Processor[] = " Processor";
@ -88,6 +89,11 @@ CONST CHAR8 ROMDATA str_x_Processor[] = "x Processor";
CONST CHAR8 ROMDATA str_L_Processor[] = "L Processor";
CONST CHAR8 ROMDATA str_N_Processor[] = "N Processor";
CONST CHAR8 ROMDATA str_R_Processor[] = "R Processor";
CONST CHAR8 ROMDATA str_E_Processor[] = "E Processor";
CONST CHAR8 ROMDATA str_0D_APU[] = "0D APU with Radeon(tm) HD Graphics";
CONST CHAR8 ROMDATA str_0_APU[] = "0 APU with Radeon(tm) HD Graphics";
CONST CHAR8 ROMDATA str_5_APU[] = "5 APU with Radeon(tm) HD Graphics";
CONST CHAR8 ROMDATA str_APU[] = " APU with Radeon(tm) HD Graphics";
/*---------------------------------------------------------------------------------------
* T Y P E D E F S, S T R U C T U R E S, E N U M S
@ -101,6 +107,7 @@ CONST AMD_CPU_BRAND ROMDATA CpuF14OnBrandIdString1ArrayFt1[] =
{2, 0, 1, ON_SOCKET_FT1, str_AMD_C, sizeof (str_AMD_C)},
{1, 0, 2, ON_SOCKET_FT1, str_AMD_E, sizeof (str_AMD_E)},
{2, 0, 2, ON_SOCKET_FT1, str_AMD_E, sizeof (str_AMD_E)},
{2, 0, 3, ON_SOCKET_FT1, str_AMD_Z, sizeof (str_AMD_Z)},
{1, 0, 4, ON_SOCKET_FT1, str_AMD_G_T, sizeof (str_AMD_G_T)},
{2, 0, 4, ON_SOCKET_FT1, str_AMD_G_T, sizeof (str_AMD_G_T)}
}; //Cores, page, index, socket, stringstart, stringlength
@ -126,6 +133,15 @@ CONST AMD_CPU_BRAND ROMDATA CpuF14OnBrandIdString2ArrayFt1[] =
{1, 0, 0x08, ON_SOCKET_FT1, str_N_Processor, sizeof (str_N_Processor)},
{2, 0, 0x08, ON_SOCKET_FT1, str_N_Processor, sizeof (str_N_Processor)},
{1, 0, 0x09, ON_SOCKET_FT1, str_R_Processor, sizeof (str_R_Processor)},
{2, 0, 0x09, ON_SOCKET_FT1, str_0_APU, sizeof (str_0_APU)},
{1, 0, 0x0A, ON_SOCKET_FT1, str_0_APU, sizeof (str_0_APU)},
{2, 0, 0x0A, ON_SOCKET_FT1, str_5_APU, sizeof (str_5_APU)},
{1, 0, 0x0B, ON_SOCKET_FT1, str_5_APU, sizeof (str_5_APU)},
{2, 0, 0x0B, ON_SOCKET_FT1, str_APU, sizeof (str_APU)},
{1, 0, 0x0C, ON_SOCKET_FT1, str_APU, sizeof (str_APU)},
{2, 0, 0x0C, ON_SOCKET_FT1, str_E_Processor, sizeof (str_E_Processor)},
{1, 0, 0x0D, ON_SOCKET_FT1, str_0D_APU, sizeof (str_0D_APU)},
{2, 0, 0x0D, ON_SOCKET_FT1, str_0D_APU, sizeof (str_0D_APU)},
{1, 0, 0x0F, ON_SOCKET_FT1, 0, 0}, //Size 0 for no suffix
{2, 0, 0x0F, ON_SOCKET_FT1, 0, 0}, //Size 0 for no suffix
}; //Cores, page, index, socket, stringstart, stringlength

8
src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14CacheDefaults.c
View File

@ -69,6 +69,14 @@
*----------------------------------------------------------------------------------------
*/
VOID
GetF14CacheInfo (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
OUT CONST VOID **CacheInfoPtr,
OUT UINT8 *NumberOfElements,
IN AMD_CONFIG_PARAMS *StdHeader
);
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------

68
src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14Dmi.c
View File

@ -76,6 +76,33 @@ extern CPU_FAMILY_SUPPORT_TABLE PstateFamilyServiceTable;
*----------------------------------------------------------------------------------------
*/
VOID
DmiF14GetInfo (
IN OUT CPU_TYPE_INFO *CpuInfoPtr,
IN AMD_CONFIG_PARAMS *StdHeader
);
UINT8
DmiF14GetVoltage (
IN AMD_CONFIG_PARAMS *StdHeader
);
UINT16
DmiF14GetMaxSpeed (
IN AMD_CONFIG_PARAMS *StdHeader
);
UINT16
DmiF14GetExtClock (
IN AMD_CONFIG_PARAMS *StdHeader
);
VOID
DmiF14GetMemInfo (
IN OUT CPU_GET_MEM_INFO *CpuGetMemInfoPtr,
IN AMD_CONFIG_PARAMS *StdHeader
);
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
@ -147,16 +174,25 @@ DmiF14GetVoltage (
{
UINT8 MaxVid;
UINT8 Voltage;
UINT8 NumberBoostStates;
UINT64 MsrData;
PCI_ADDR TempAddr;
CPU_LOGICAL_ID CpuFamilyRevision;
CPB_CTRL_REGISTER CpbCtrl;
// Voltage = 0x80 + (voltage at boot time * 10)
LibAmdMsrRead (MSR_COFVID_STS, &MsrData, StdHeader);
MaxVid = (UINT8) (((COFVID_STS_MSR *)&MsrData)->MaxVid);
if (MaxVid == 0) {
LibAmdMsrRead (MSR_PSTATE_0, &MsrData, StdHeader);
MaxVid = (UINT8) (((PSTATE_MSR *)&MsrData)->CpuVid);
GetLogicalIdOfCurrentCore (&CpuFamilyRevision, StdHeader);
if ((CpuFamilyRevision.Revision & (AMD_F14_ON_Ax | AMD_F14_ON_Bx)) == 0) {
TempAddr.AddressValue = CPB_CTRL_PCI_ADDR;
LibAmdPciRead (AccessWidth32, TempAddr, &CpbCtrl, StdHeader); // F4x15C
NumberBoostStates = (UINT8) CpbCtrl.NumBoostStates;
} else {
NumberBoostStates = 0;
}
LibAmdMsrRead ((MSR_PSTATE_0 + NumberBoostStates), &MsrData, StdHeader);
MaxVid = (UINT8) (((PSTATE_MSR *)&MsrData)->CpuVid);
if ((MaxVid >= 0x7C) && (MaxVid <= 0x7F)) {
Voltage = 0;
} else {
@ -184,14 +220,27 @@ DmiF14GetMaxSpeed (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT8 NumBoostStates;
UINT32 P0Frequency;
UINT32 PciData;
PCI_ADDR PciAddress;
PSTATE_CPU_FAMILY_SERVICES *FamilyServices;
CPU_LOGICAL_ID CpuFamilyRevision;
FamilyServices = NULL;
GetFeatureServicesOfCurrentCore (&PstateFamilyServiceTable, &FamilyServices, StdHeader);
GetFeatureServicesOfCurrentCore (&PstateFamilyServiceTable, (const VOID **)&FamilyServices, StdHeader);
ASSERT (FamilyServices != NULL);
FamilyServices->GetPstateFrequency (FamilyServices, (UINT8) 0x00, &P0Frequency, StdHeader);
GetLogicalIdOfCurrentCore (&CpuFamilyRevision, StdHeader);
if ((CpuFamilyRevision.Revision & (AMD_F14_ON_Ax | AMD_F14_ON_Bx)) == 0) {
PciAddress.AddressValue = MAKE_SBDFO (0, 0 , PCI_DEV_BASE, FUNC_4, 0x15C);
LibAmdPciRead (AccessWidth32, PciAddress, &PciData, StdHeader);
NumBoostStates = (UINT8) ((PciData >> 2) & 7);
} else {
NumBoostStates = 0;
}
FamilyServices->GetPstateFrequency (FamilyServices, NumBoostStates, &P0Frequency, StdHeader);
return ((UINT16) P0Frequency);
}
@ -242,6 +291,10 @@ DmiF14GetMemInfo (
* Processor Family Table
*
* Note: 'x' means we don't care this field
* 046h = "AMD C-Series Processor"
* 047h = "AMD E-Series Processor"
* 048h = "AMD S-Series Processor"
* 049h = "AMD G-Series Processor"
* 002h = "Unknown"
*-------------------------------------------------------------------------------------*/
CONST DMI_BRAND_ENTRY ROMDATA Family14BrandList[] =
@ -250,6 +303,7 @@ CONST DMI_BRAND_ENTRY ROMDATA Family14BrandList[] =
// PackageType, PgOfBrandId, NumberOfCores, String1ofBrandId, ValueSetToDmiTable
{0, 0, 'x', 1, 0x46},
{0, 0, 'x', 2, 0x47},
{0, 0, 'x', 4, 0x49},
{'x', 'x', 'x', 'x', 0x02}
};

149
src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14LowPowerInit.c Normal file
View File

@ -0,0 +1,149 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD Family_14 Optimizations for lower power consumption
*
* Sets some registers for tablet parts at AmdInitEarly.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/Family/F14
* @e \$Revision: 45578 $ @e \$Date: 2011-01-18 19:20:41 -0500 (Tue, 18 Jan 2011) $
*
*/
/*
******************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "amdlib.h"
#include "cpuFamilyTranslation.h"
#include "cpuF14PowerMgmt.h"
#include "cpuF14LowPowerInit.h"
#include "Filecode.h"
#define FILECODE PROC_CPU_FAMILY_0X14_CPUF14LOWPOWERINIT_FILECODE
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------*/
/**
* Family 14h model 0 - 0xF core 0 entry point for programming registers for lower
* power consumption.
*
* Set up D18F6x94[CpuPstateThrEn, CpuPstateThr], and D18F4x134[IntRateCC6DecrRate
* according to the BKDG.
*
* @param[in] FamilySpecificServices The current Family Specific Services.
* @param[in] CpuEarlyParams Service parameters
* @param[in] StdHeader Config handle for library and services.
*
*/
VOID
F14OptimizeForLowPowerInit (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT8 NumBoostStates;
UINT32 LocalPciRegister;
BOOLEAN OptimizeForLowPower;
BOOLEAN IsRevC;
PCI_ADDR PciAddress;
CPU_LOGICAL_ID CpuFamilyRevision;
PciAddress.AddressValue = PRODUCT_INFO_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
if ((((PRODUCT_INFO_REGISTER *) &LocalPciRegister)->LowPowerDefault == 1) &&
(CpuEarlyParams->PlatformConfig.PlatformProfile.PlatformPowerPolicy == BatteryLife)) {
OptimizeForLowPower = TRUE;
} else {
OptimizeForLowPower = FALSE;
}
// Get F4x15C [4:2] NumBoostStates
// Get IsRevC
NumBoostStates = 0;
IsRevC = FALSE;
GetLogicalIdOfCurrentCore (&CpuFamilyRevision, StdHeader);
if ((CpuFamilyRevision.Revision & AMD_F14_ON_Cx) != 0) {
IsRevC = TRUE;
PciAddress.AddressValue = CPB_CTRL_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
NumBoostStates = (UINT8) ((CPB_CTRL_REGISTER *) &LocalPciRegister)->NumBoostStates;
}
// F6x94[2:0] CpuPstateThr
PciAddress.AddressValue = NB_PSTATE_CFG_HIGH_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
if (OptimizeForLowPower) {
((NB_PSTATE_CFG_HIGH_REGISTER *) &LocalPciRegister)->CpuPstateThr = 0;
} else {
if (NumBoostStates == 0) {
((NB_PSTATE_CFG_HIGH_REGISTER *) &LocalPciRegister)->CpuPstateThr = 1;
} else {
((NB_PSTATE_CFG_HIGH_REGISTER *) &LocalPciRegister)->CpuPstateThr = 2;
}
}
// F6x94[3] CpuPstateThrEn = 1
((NB_PSTATE_CFG_HIGH_REGISTER *) &LocalPciRegister)->CpuPstateThrEn = 1;
LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
// F4x134[31:27] IntRateCC6DecrRate
PciAddress.AddressValue = CSTATE_MON_CTRL3_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
((CSTATE_MON_CTRL3_REGISTER *) &LocalPciRegister)->IntRateCC6DecrRate = (OptimizeForLowPower || IsRevC) ? 0x18 : 0x8;
LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
}

77
src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14LowPowerInit.h Normal file
View File

@ -0,0 +1,77 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD Family_14 Optimizations for Low Power
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/Family/F14
* @e \$Revision: 45578 $ @e \$Date: 2011-01-18 19:20:41 -0500 (Tue, 18 Jan 2011) $
*
*/
/*
******************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#ifndef _F14_LOW_POWER_INIT_H_
#define _F14_LOW_POWER_INIT_H_
/*---------------------------------------------------------------------------------------
* M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
*---------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*---------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------
* T Y P E D E F S, S T R U C T U R E S, E N U M S
*---------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------
* F U N C T I O N P R O T O T Y P E
*---------------------------------------------------------------------------------------
*/
VOID
F14OptimizeForLowPowerInit (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams,
IN AMD_CONFIG_PARAMS *StdHeader
);
#endif // _F14_LOW_POWER_INIT_H_

59
src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14MsrTables.c
View File

@ -7,7 +7,7 @@
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU
* @e \$Revision: 37263 $ @e \$Date: 2010-09-01 21:58:26 +0800 (Wed, 01 Sep 2010) $
* @e \$Revision: 48588 $ @e \$Date: 2011-03-10 08:57:36 -0700 (Thu, 10 Mar 2011) $
*
*/
/*
@ -77,6 +77,21 @@ CONST MSR_TYPE_ENTRY_INITIALIZER ROMDATA F14MsrRegisters[] =
// M S R T a b l e s
// ----------------------
// MC0_CTL_MASK (0xC0010044)
// bit[6] = 1, erratum #628
{
MsrRegister,
{
AMD_FAMILY_14, // CpuFamily
AMD_F14_ON_ALL // CpuRevision
},
{AMD_PF_ALL}, // platformFeatures
{{
MSR_MC0_CTL_MASK, // MSR Address
0x0000000000000040, // OR Mask
0x0000000000000040, // NAND Mask
}}
},
// MSR_TOM2 (0xC001001D)
// bits[63:0] - TOP_MEM2 = 0
{
@ -85,12 +100,12 @@ CONST MSR_TYPE_ENTRY_INITIALIZER ROMDATA F14MsrRegisters[] =
AMD_FAMILY_14, // CpuFamily
AMD_F14_ALL // CpuRevision
},
AMD_PF_ALL, // platformFeatures
{
{AMD_PF_ALL}, // platformFeatures
{{
MSR_TOM2, // MSR Address
0x0000000000000000, // OR Mask
0xFFFFFFFFFFFFFFFF, // NAND Mask
}
}}
},
// MSR_SYS_CFG (0xC0010010)
// bit[21] - MtrrTom2En = 1
@ -100,12 +115,12 @@ CONST MSR_TYPE_ENTRY_INITIALIZER ROMDATA F14MsrRegisters[] =
AMD_FAMILY_14, // CpuFamily
AMD_F14_ALL // CpuRevision
},
AMD_PF_ALL, // platformFeatures
{
{AMD_PF_ALL}, // platformFeatures
{{
MSR_SYS_CFG, // MSR Address
(1 << 21), // OR Mask
(1 << 21), // NAND Mask
}
}}
},
// MSR_CPUID_EXT_FEATS (0xC0011005)
// bit[41] - OSVW = 0
@ -115,12 +130,12 @@ CONST MSR_TYPE_ENTRY_INITIALIZER ROMDATA F14MsrRegisters[] =
AMD_FAMILY_14, // CpuFamily
AMD_F14_ALL // CpuRevision
},
AMD_PF_ALL, // platformFeatures
{
{AMD_PF_ALL}, // platformFeatures
{{
MSR_CPUID_EXT_FEATS, // MSR Address
0x0000000000000000, // OR Mask
0x0000020000000000, // NAND Mask
}
}}
},
// MSR_OSVW_ID_Length (0xC0010140)
// bit[15:0] = 4
@ -130,12 +145,12 @@ CONST MSR_TYPE_ENTRY_INITIALIZER ROMDATA F14MsrRegisters[] =
AMD_FAMILY_14, // CpuFamily
AMD_F14_ALL // CpuRevision
},
AMD_PF_ALL, // platformFeatures
{
{AMD_PF_ALL}, // platformFeatures
{{
MSR_OSVW_ID_Length, // MSR Address
0x0000000000000004, // OR Mask
0x000000000000FFFF, // NAND Mask
}
}}
},
// MSR_HWCR (0xC0010015)
// Do not set bit[24] = 1, it will be set in AmdInitPost.
@ -149,12 +164,12 @@ CONST MSR_TYPE_ENTRY_INITIALIZER ROMDATA F14MsrRegisters[] =
AMD_FAMILY_14, // CpuFamily
AMD_F14_ALL // CpuRevision
},
AMD_PF_ALL, // platformFeatures
{
{AMD_PF_ALL}, // platformFeatures
{{
MSR_MC0_CTL, // MSR Address
0xFFFFFFFFFFFFFFFF, // OR Mask
0xFFFFFFFFFFFFFFFF, // NAND Mask
}
}}
},
// MSR_LS_CFG (0xC0011020)
// bit[36] Reserved = 1, workaround for erratum #530
@ -165,12 +180,12 @@ CONST MSR_TYPE_ENTRY_INITIALIZER ROMDATA F14MsrRegisters[] =
AMD_FAMILY_14, // CpuFamily
AMD_F14_ALL // CpuRevision
},
AMD_PF_ALL, // platformFeatures
{
{AMD_PF_ALL}, // platformFeatures
{{
MSR_LS_CFG, // MSR Address
0x0000001002000000, // OR Mask
0x0000001002000000, // NAND Mask
}
}}
},
// MSR_DC_CFG (0xC0011022)
// bit[57:56] Reserved = 2
@ -180,12 +195,12 @@ CONST MSR_TYPE_ENTRY_INITIALIZER ROMDATA F14MsrRegisters[] =
AMD_FAMILY_14, // CpuFamily
AMD_F14_ALL // CpuRevision
},
AMD_PF_ALL, // platformFeatures
{
{AMD_PF_ALL}, // platformFeatures
{{
MSR_DC_CFG, // MSR Address
0x0200000000000000, // OR Mask
0x0300000000000000, // NAND Mask
}
}}
}
};

231
src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14PciTables.c
View File

@ -89,12 +89,12 @@ STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F14PciRegisters[] =
AMD_FAMILY_14, // CpuFamily
AMD_F14_ALL // CpuRevision
},
AMD_PF_ALL, // platformFeatures
{
{AMD_PF_ALL}, // platformFeatures
{{
MAKE_SBDFO (0, 0, 24, FUNC_0, 0x68), // Address
0x002E0800, // regData
0x006E0800, // regMask
}
}}
},
// Function 2 - DRAM Controller
@ -106,12 +106,12 @@ STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F14PciRegisters[] =
AMD_FAMILY_14, // CpuFamily
AMD_F14_ALL // CpuRevision
},
AMD_PF_ALL, // platformFeatures
{
{AMD_PF_ALL}, // platformFeatures
{{
MAKE_SBDFO (0, 0, 24, FUNC_2, 0xB8), // Address
0x00000000, // regData
0xF000F000, // regMask
}
}}
},
// D18F2xBC
{
@ -120,12 +120,12 @@ STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F14PciRegisters[] =
AMD_FAMILY_14, // CpuFamily
AMD_F14_ALL // CpuRevision
},
AMD_PF_ALL, // platformFeatures
{
{AMD_PF_ALL}, // platformFeatures
{{
MAKE_SBDFO (0, 0, 24, FUNC_2, 0xBC), // Address
0x00000000, // regData
0xC0000000, // regMask
}
}}
},
// D18F2x118 - Memory Controller Configuration Low
// bits[7:6], MctPriHiWr = 10b
@ -135,12 +135,12 @@ STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F14PciRegisters[] =
AMD_FAMILY_14, // CpuFamily
AMD_F14_ALL // CpuRevision
},
AMD_PF_ALL, // platformFeatures
{
{AMD_PF_ALL}, // platformFeatures
{{
MAKE_SBDFO (0, 0, 24, FUNC_2, 0x118), // Address
0x00000080, // regData
0x000000C0, // regMask
}
}}
},
// D18F2x11C - Memory Controller Configuration High
// bits[24:22], PrefConf = 1
@ -150,12 +150,12 @@ STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F14PciRegisters[] =
AMD_FAMILY_14, // CpuFamily
AMD_F14_ALL // CpuRevision
},
AMD_PF_ALL, // platformFeatures
{
{AMD_PF_ALL}, // platformFeatures
{{
MAKE_SBDFO (0, 0, 24, FUNC_2, 0x11C), // Address
0x00400000, // regData
0x01C00000, // regMask
}
}}
},
// Function 3 - Misc. Control
@ -168,12 +168,12 @@ STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F14PciRegisters[] =
AMD_FAMILY_14, // CpuFamily
AMD_F14_ALL // CpuRevision
},
AMD_PF_ALL, // platformFeatures
{
{AMD_PF_ALL}, // platformFeatures
{{
MAKE_SBDFO (0, 0, 24, FUNC_3, 0x40), // Address
0x00000100, // regData
0x00000100, // regMask
}
}}
},
// D18F3x44 - MCA NB Configuration
// bit[27] NbMcaToMstCpuEn = 1
@ -189,12 +189,12 @@ STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F14PciRegisters[] =
AMD_FAMILY_14, // CpuFamily
AMD_F14_ALL // CpuRevision
},
AMD_PF_ALL, // platformFeatures
{
{AMD_PF_ALL}, // platformFeatures
{{
MAKE_SBDFO (0, 0, 24, FUNC_3, 0x44), // Address
0x0A300040, // regData
0x0A303E40, // regMask
}
}}
},
// D18F3x84 - ACPI Power State Control High
// bit[18] Smaf6DramMemClkTri = 1
@ -207,12 +207,12 @@ STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F14PciRegisters[] =
AMD_FAMILY_14, // CpuFamily
AMD_F14_ALL // CpuRevision
},
AMD_PF_ALL, // platformFeatures
{
{AMD_PF_ALL}, // platformFeatures
{{
MAKE_SBDFO (0, 0, 24, FUNC_3, 0x84), // Address
0x00060006, // regData
0x00060006, // regMask
}
}}
},
// D18F3x8C - NB Configuration High
// bit[26] EnConvertToNonIsoc = 1
@ -222,12 +222,12 @@ STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F14PciRegisters[] =
AMD_FAMILY_14, // CpuFamily
AMD_F14_ALL // CpuRevision
},
AMD_PF_ALL, // platformFeatures
{
{AMD_PF_ALL}, // platformFeatures
{{
MAKE_SBDFO (0, 0, 24, FUNC_3, 0x8C), // Address
0x04000000, // regData
0x04000000, // regMask
}
}}
},
// D18F3xA0 - Power Control Miscellaneous
// bit[9] SviHighFreqSel = 1
@ -237,12 +237,12 @@ STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F14PciRegisters[] =
AMD_FAMILY_14, // CpuFamily
AMD_F14_ALL // CpuRevision
},
AMD_PF_ALL, // platformFeatures
{
{AMD_PF_ALL}, // platformFeatures
{{
MAKE_SBDFO (0, 0, 24, FUNC_3, 0xA0), // Address
0x00000200, // regData
0x00000200, // regMask
}
}}
},
// D18F3xA4 - Reported Temperature Control
// bits[12:8] PerStepTimeDn = 0xF
@ -256,12 +256,12 @@ STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F14PciRegisters[] =
AMD_FAMILY_14, // CpuFamily
AMD_F14_ALL // CpuRevision
},
AMD_PF_ALL, // platformFeatures
{
{AMD_PF_ALL}, // platformFeatures
{{
MAKE_SBDFO (0, 0, 24, FUNC_3, 0xA4), // Address
0x00000FEF, // regData
0x00001FFF, // regMask
}
}}
},
// D18F3xD4 - Clock Power Timing Control 0
// bits[11:8] ClkRampHystSel = 0xF
@ -273,16 +273,16 @@ STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F14PciRegisters[] =
AMD_FAMILY_14, // CpuFamily
AMD_F14_ALL // CpuRevision
},
AMD_PF_ALL, // platformFeatures
{
{AMD_PF_ALL}, // platformFeatures
{{
MAKE_SBDFO (0, 0, 24, FUNC_3, 0xD4), // Address
0x00024F00, // regData
0x0002FF00, // regMask
}
}}
},
// D18F3xDC - Clock Power Timing Control 2
// bits[29:27] NbClockGateHyst = 3
// bit[30] NbClockGateEn = 1
// bit[30] NbClockGateEn = 0 - erratum #596
// bit[31] CnbCifClockGateEn = 1
{
PciRegister,
@ -290,12 +290,12 @@ STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F14PciRegisters[] =
AMD_FAMILY_14, // CpuFamily
AMD_F14_ALL // CpuRevision
},
AMD_PF_ALL, // platformFeatures
{
{AMD_PF_ALL}, // platformFeatures
{{
MAKE_SBDFO (0, 0, 24, FUNC_3, 0xDC), // Address
0xD8000000, // regData
0x98000000, // regData
0xF8000000, // regMask
}
}}
},
// D18F3x180 - Extended NB MCA Configuration
// bit[2] WDTCntSel[3] = 0
@ -307,12 +307,12 @@ STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F14PciRegisters[] =
AMD_FAMILY_14, // CpuFamily
AMD_F14_ALL // CpuRevision
},
AMD_PF_ALL, // platformFeatures
{
{AMD_PF_ALL}, // platformFeatures
{{
MAKE_SBDFO (0, 0, 24, FUNC_3, 0x180), // Address
0x00200020, // regData
0x00200024, // regMask
}
}}
},
// D18F3x188 - NB Extended Configuration
// bit[21] EnCpuSerWrBehindIoRd = 0
@ -325,12 +325,12 @@ STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F14PciRegisters[] =
AMD_FAMILY_14, // CpuFamily
AMD_F14_ALL // CpuRevision
},
AMD_PF_ALL, // platformFeatures
{
{AMD_PF_ALL}, // platformFeatures
{{
MAKE_SBDFO (0, 0, 24, FUNC_3, 0x188), // Address
0x1B000000, // regData
0xFFA00000, // regMask
}
}}
},
// Function 4 - Extended Misc. Control
@ -344,12 +344,12 @@ STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F14PciRegisters[] =
AMD_FAMILY_14, // CpuFamily
AMD_F14_ALL // CpuRevision
},
AMD_PF_ALL, // platformFeatures
{
{AMD_PF_ALL}, // platformFeatures
{{
MAKE_SBDFO (0, 0, 24, FUNC_4, 0x118), // Address
0x00000000, // regData
0x00000707, // regMask
}
}}
},
// D18F4x124 - C-state Monitor Control 1
// bit[15] TimerTickIntvlScale = 1
@ -364,12 +364,12 @@ STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F14PciRegisters[] =
AMD_FAMILY_14, // CpuFamily
AMD_F14_ALL // CpuRevision
},
AMD_PF_ALL, // platformFeatures
{
{AMD_PF_ALL}, // platformFeatures
{{
MAKE_SBDFO (0, 0, 24, FUNC_4, 0x124), // Address
0x05138000, // regData
0x07FF8000, // regMask
}
}}
},
// D18F4x134 - C-state Monitor Control 3
// bits[3:0] IntRatePkgC6MaxDepth = 0
@ -379,19 +379,18 @@ STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F14PciRegisters[] =
// bits[19:16] IntRateCC6MaxDepth = 5
// bits[23:20] IntRateCC6Threshold = 4
// bits[26:24] IntRateCC6BurstLen = 5
// bits[31:27] IntRateCC6DecrRate = 0x08
{
PciRegister,
{
AMD_FAMILY_14, // CpuFamily
AMD_F14_ALL // CpuRevision
},
AMD_PF_ALL, // platformFeatures
{
{AMD_PF_ALL}, // platformFeatures
{{
MAKE_SBDFO (0, 0, 24, FUNC_4, 0x134), // Address
0x45455100, // regData
0xFFFFFFFF, // regMask
}
0x05455100, // regData
0x07FFFFFF, // regMask
}}
},
// D18F4x13C - SMAF Code DID 1
// bits[4:0] Smaf4Did = 0x0F
@ -402,12 +401,12 @@ STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F14PciRegisters[] =
AMD_FAMILY_14, // CpuFamily
AMD_F14_ALL // CpuRevision
},
AMD_PF_ALL, // platformFeatures
{
{AMD_PF_ALL}, // platformFeatures
{{
MAKE_SBDFO (0, 0, 24, FUNC_4, 0x13C), // Address
0x000F000F, // regData
0x001F001F, // regMask
}
}}
},
// D18F4x1A4 - C-state Monitor Mask
// bits[7:0] IntRateMonMask = 0xFC
@ -420,12 +419,12 @@ STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F14PciRegisters[] =
AMD_FAMILY_14, // CpuFamily
AMD_F14_ALL // CpuRevision
},
AMD_PF_ALL, // platformFeatures
{
{AMD_PF_ALL}, // platformFeatures
{{
MAKE_SBDFO (0, 0, 24, FUNC_4, 0x1A4), // Address
0xFFFFFFFC, // regData
0xFFFFFFFF, // regMask
}
}}
},
// D18F4x1A8 - CPU State Power Management Dynamic Control 0
// bits[4:0] SingleHaltCpuDid = 0x1E
@ -439,12 +438,12 @@ STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F14PciRegisters[] =
AMD_FAMILY_14, // CpuFamily
AMD_F14_ALL // CpuRevision
},
AMD_PF_ALL, // platformFeatures
{
{AMD_PF_ALL}, // platformFeatures
{{
MAKE_SBDFO (0, 0, 24, FUNC_4, 0x1A8), // Address
0x009003FE, // regData
0x00F083FF, // regMask
}
}}
},
// D18F4x1AC - CPU State Power Management Dynamic Control 1
// bits[9:5] C6Did = 0x1F
@ -456,12 +455,12 @@ STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F14PciRegisters[] =
AMD_FAMILY_14, // CpuFamily
AMD_F14_ALL // CpuRevision
},
AMD_PF_ALL, // platformFeatures
{
{AMD_PF_ALL}, // platformFeatures
{{
MAKE_SBDFO (0, 0, 24, FUNC_4, 0x1AC), // Address
0x300003E0, // regData
0x300003E0, // regMask
}
}}
},
// D18F6x50 - Configuration Register Access Control
// bit[1] CfgAccAddrMode = 0
@ -471,12 +470,12 @@ STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F14PciRegisters[] =
AMD_FAMILY_14, // CpuFamily
AMD_F14_ALL // CpuRevision
},
AMD_PF_ALL, // platformFeatures
{
{AMD_PF_ALL}, // platformFeatures
{{
MAKE_SBDFO (0, 0, 24, FUNC_6, 0x50), // Address
0x00000000, // regData
0x00000002, // regMask
}
}}
},
// D18F6x54 - DRAM Arbitration Control FEQ Collision
// bits[7:0] FeqLoPrio = 0x20
@ -489,12 +488,12 @@ STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F14PciRegisters[] =
AMD_FAMILY_14, // CpuFamily
AMD_F14_ALL // CpuRevision
},
AMD_PF_ALL, // platformFeatures
{
{AMD_PF_ALL}, // platformFeatures
{{
MAKE_SBDFO (0, 0, 24, FUNC_6, 0x54), // Address
0x00081020, // regData
0x80FFFFFF, // regMask
}
}}
},
// D18F6x58 - DRAM Arbitration Control Display Collision
// bits[7:0] DispLoPrio = 0x40
@ -507,12 +506,12 @@ STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F14PciRegisters[] =
AMD_FAMILY_14, // CpuFamily
AMD_F14_ALL // CpuRevision
},
AMD_PF_ALL, // platformFeatures
{
{AMD_PF_ALL}, // platformFeatures
{{
MAKE_SBDFO (0, 0, 24, FUNC_6, 0x58), // Address
0x00102040, // regData
0xFFFFFFFF, // regMask
}
}}
},
// D18F6x5C - DRAM Arbitration Control FEQ Write Protect
// bits[7:0] FeqLoPrio = 0x20
@ -525,12 +524,12 @@ STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F14PciRegisters[] =
AMD_FAMILY_14, // CpuFamily
AMD_F14_ALL // CpuRevision
},
AMD_PF_ALL, // platformFeatures
{
{AMD_PF_ALL}, // platformFeatures
{{
MAKE_SBDFO (0, 0, 24, FUNC_6, 0x5C), // Address
0x00081020, // regData
0x80FFFFFF, // regMask
}
}}
},
// D18F6x60 - DRAM Arbitration Control Display Write Protect
// bits[7:0] DispLoPri = 0x20
@ -543,12 +542,12 @@ STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F14PciRegisters[] =
AMD_FAMILY_14, // CpuFamily
AMD_F14_ALL // CpuRevision
},
AMD_PF_ALL, // platformFeatures
{
{AMD_PF_ALL}, // platformFeatures
{{
MAKE_SBDFO (0, 0, 24, FUNC_6, 0x60), // Address
0x00081020, // regData
0xFFFFFFFF, // regMask
}
}}
},
// D18F6x64 - DRAM Arbitration Control FEQ Read Protect
// bits[7:0] FeqLoPrio = 0x10
@ -561,12 +560,12 @@ STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F14PciRegisters[] =
AMD_FAMILY_14, // CpuFamily
AMD_F14_ALL // CpuRevision
},
AMD_PF_ALL, // platformFeatures
{
{AMD_PF_ALL}, // platformFeatures
{{
MAKE_SBDFO (0, 0, 24, FUNC_6, 0x64), // Address
0x00040810, // regData
0x80FFFFFF, // regMask
}
}}
},
// D18F6x68 - DRAM Arbitration Control Display Read Protect
// bits[7:0] DispLoPrio = 0x10
@ -579,12 +578,12 @@ STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F14PciRegisters[] =
AMD_FAMILY_14, // CpuFamily
AMD_F14_ALL // CpuRevision
},
AMD_PF_ALL, // platformFeatures
{
{AMD_PF_ALL}, // platformFeatures
{{
MAKE_SBDFO (0, 0, 24, FUNC_6, 0x68), // Address
0x00040810, // regData
0xFFFFFFFF, // regMask
}
}}
},
// D18F6x6C - DRAM Arbitration Control FEQ Fairness Timer
// bits[7:0] FeqLoPrio = 0x80
@ -596,12 +595,12 @@ STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F14PciRegisters[] =
AMD_FAMILY_14, // CpuFamily
AMD_F14_ALL // CpuRevision
},
AMD_PF_ALL, // platformFeatures
{
{AMD_PF_ALL}, // platformFeatures
{{
MAKE_SBDFO (0, 0, 24, FUNC_6, 0x6C), // Address
0x00204080, // regData
0x00FFFFFF, // regMask
}
}}
},
// D18F6x70 - DRAM Arbitration Control Display Fairness Timer
// bits[7:0] DispLoPrio = 0x80
@ -614,12 +613,12 @@ STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F14PciRegisters[] =
AMD_FAMILY_14, // CpuFamily
AMD_F14_ALL // CpuRevision
},
AMD_PF_ALL, // platformFeatures
{
{AMD_PF_ALL}, // platformFeatures
{{
MAKE_SBDFO (0, 0, 24, FUNC_6, 0x70), // Address
0x00204080, // regData
0xFFFFFFFF, // regMask
}
}}
},
// D18F6x74 - Dram Idle Page Close Limit
// bits[40] IdleLimit = 0x1E
@ -629,12 +628,12 @@ STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F14PciRegisters[] =
AMD_FAMILY_14, // CpuFamily
AMD_F14_ALL // CpuRevision
},
AMD_PF_ALL, // platformFeatures
{
{AMD_PF_ALL}, // platformFeatures
{{
MAKE_SBDFO (0, 0, 24, FUNC_6, 0x74), // Address
0x0000001E, // regData
0x0000001F, // regMask
}
}}
},
// D18F6x78 - Dram Prioritization and Arbitration Control
// bits[1:0] DispDbePrioEn = 3
@ -648,12 +647,12 @@ STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F14PciRegisters[] =
AMD_FAMILY_14, // CpuFamily
AMD_F14_ALL // CpuRevision
},
AMD_PF_ALL, // platformFeatures
{
{AMD_PF_ALL}, // platformFeatures
{{
MAKE_SBDFO (0, 0, 24, FUNC_6, 0x78), // Address
0x00000037, // regData
0x0000007F, // regMask
}
}}
},
// D18F6x90 - NB P-state Config Low
// As part of BIOS Requirements for NB P-state Initialization
@ -666,16 +665,14 @@ STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F14PciRegisters[] =
AMD_FAMILY_14, // CpuFamily
AMD_F14_ALL // CpuRevision
},
AMD_PF_ALL, // platformFeatures
{
{AMD_PF_ALL}, // platformFeatures
{{
MAKE_SBDFO (0, 0, 24, FUNC_6, 0x90), // Address
0x50000000, // regData
0x70000000, // regMask
}
}}
},
// D18F6x94 - NB P-state Config High
// bits[2:0] CpuPstateThr = 1
// bit[3] CpuPstateThrEn = 1
// bits[25:23] NbPsC0Timer = 4
{
PciRegister,
@ -683,12 +680,12 @@ STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F14PciRegisters[] =
AMD_FAMILY_14, // CpuFamily
AMD_F14_ALL // CpuRevision
},
AMD_PF_ALL, // platformFeatures
{
{AMD_PF_ALL}, // platformFeatures
{{
MAKE_SBDFO (0, 0, 24, FUNC_6, 0x94), // Address
0x02000009, // regData
0x0380000F, // regMask
}
0x02000000, // regData
0x03800000, // regMask
}}
},
// D18F6x9C - NCLK Reduction Control
// bits[6:0] NclkRedDiv = 0x60
@ -700,12 +697,12 @@ STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F14PciRegisters[] =
AMD_FAMILY_14, // CpuFamily
AMD_F14_ALL // CpuRevision
},
AMD_PF_ALL, // platformFeatures
{
{AMD_PF_ALL}, // platformFeatures
{{
MAKE_SBDFO (0, 0, 24, FUNC_6, 0x9C), // Address
0x000001E0, // regData
0x000001FF, // regMask
}
}}
}
};

6
src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14PerCorePciTables.c
View File

@ -86,12 +86,12 @@ STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F14PerCorePciRegisters[] =
AMD_FAMILY_14, // CpuFamily
AMD_F14_ALL // CpuRevision
},
AMD_PF_ALL, // platformFeatures
{
{AMD_PF_ALL}, // platformFeatures
{{
MAKE_SBDFO (0, 0, 24, FUNC_3, 0x1CC), // Address
0x00000100, // regData
0x0000010F, // regMask
}
}}
}
};

218
src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14PowerCheck.c
View File

@ -10,7 +10,7 @@
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/F14
* @e \$Revision: 39744 $ @e \$Date: 2010-10-15 02:18:02 +0800 (Fri, 15 Oct 2010) $
* @e \$Revision: 46951 $ @e \$Date: 2011-02-11 12:37:59 -0700 (Fri, 11 Feb 2011) $
*
*/
/*
@ -51,7 +51,6 @@
*/
#include "AGESA.h"
#include "amdlib.h"
#include "cpuCacheInit.h"
#include "cpuF14PowerMgmt.h"
#include "cpuRegisters.h"
#include "cpuApicUtilities.h"
@ -60,7 +59,6 @@
#include "cpuEarlyInit.h"
#include "cpuFamilyTranslation.h"
#include "cpuF14PowerCheck.h"
#include "cpuF14Utilities.h"
#include "Filecode.h"
#define FILECODE PROC_CPU_FAMILY_0X14_CPUF14POWERCHECK_FILECODE
@ -100,18 +98,18 @@ F14PmPwrChkCopyPstate (
/*---------------------------------------------------------------------------------------*/
/**
* Family 14h core 0 entry point for performing the family 14h Processor-
* Family 14h Ontario core 0 entry point for performing the family 14h Ontario Processor-
* Systemboard Power Delivery Check.
*
* The steps are as follows:
* 1. Starting with P0, loop through all P-states until a passing state is
* 1. Starting with hardware P0, loop through all P-states until a passing state is
* found. A passing state is one in which the current required by the
* CPU is less than the maximum amount of current that the system can
* provide to the CPU. If P0 is under the limit, no further action is
* necessary.
* 2. If at least one P-State is under the limit & at least one P-State is
* over the limit, the BIOS must:
* a. Clear both D18F4x15C[BoostSrc] and D18F4x15C[NumBoostStates] to 0.
* a. Program D18F4x15C[BoostSrc]=0.
* b. If the processor's current P-State is disabled by the power check,
* then the BIOS must request a transition to an enabled P-state
* using MSRC001_0062[PstateCmd] and wait for MSRC001_0063[CurPstate]
@ -126,7 +124,7 @@ F14PmPwrChkCopyPstate (
* 1. D18F3x64[HtcPstateLimit]
* 2. D18F3xDC[PstateMaxVal]
* 3. If all P-States are over the limit, the BIOS must:
* a. Clear both D18F4x15C[BoostSrc] and D18F4x15C[NumBoostStates] to 0.
* a. Program D18F4x15C[BoostSrc]=0.
* b. If the processor's current P-State is != D18F3xDC[PstateMaxVal], then
* write D18F3xDC[PstateMaxVal] to MSRC001_0062[PstateCmd] and wait for
* MSRC001_0063[CurPstate] to reflect the new value.
@ -151,17 +149,24 @@ F14PmPwrCheck (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT8 DisPsNum;
UINT8 DisHwPsNum;
UINT8 DisSwPsNum;
UINT8 PsMaxVal;
UINT8 Pstate;
UINT8 PstateLimit;
UINT8 NumberBoostStates;
UINT32 ProcIddMax;
UINT32 PciRegister;
UINT32 Socket;
UINT32 Module;
UINT32 Core;
UINT32 PstateLimit;
PCI_ADDR PciAddress;
UINT64 MsrRegister;
UINT64 LocalMsrRegister;
BOOLEAN ThermalPstateEn;
NB_CAPS_REGISTER NbCaps;
HTC_REGISTER HtcReg;
CLK_PWR_TIMING_CTRL2_REGISTER ClkPwrTimingCtrl2;
CPB_CTRL_REGISTER CpbCtrl;
CPU_LOGICAL_ID CpuFamilyRevision;
AP_TASK TaskPtr;
AGESA_STATUS IgnoredSts;
PWRCHK_ERROR_DATA ErrorData;
@ -172,17 +177,53 @@ F14PmPwrCheck (
ASSERT (Core == 0);
// save ThermalPstateEn
// TRUE if the P-state indicated by D18F3x64[HtcPstateLimit] is enabled;
// FALSE otherwise.
PciAddress.AddressValue = HTC_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &HtcReg, StdHeader); // D18F3x64
LibAmdMsrRead (PS_REG_BASE + HtcReg.HtcPstateLimit, &LocalMsrRegister, StdHeader);
if (((PSTATE_MSR *) &LocalMsrRegister)->PsEnable == 1) {
ThermalPstateEn = TRUE;
} else {
ThermalPstateEn = FALSE;
}
// get the Max P-state value
for (PsMaxVal = NM_PS_REG - 1; PsMaxVal != 0; --PsMaxVal) {
LibAmdMsrRead (PS_REG_BASE + PsMaxVal, &MsrRegister, StdHeader);
if (((PSTATE_MSR *) &MsrRegister)->PsEnable == 1) {
LibAmdMsrRead (PS_REG_BASE + PsMaxVal, &LocalMsrRegister, StdHeader);
if (((PSTATE_MSR *) &LocalMsrRegister)->PsEnable == 1) {
break;
}
}
ErrorData.HwPstateNumber = (UINT8) (PsMaxVal + 1);
DisPsNum = 0;
// get NumberBoostStates
GetLogicalIdOfCurrentCore (&CpuFamilyRevision, StdHeader);
if ((CpuFamilyRevision.Revision & (AMD_F14_ON_Ax | AMD_F14_ON_Bx)) != 0) {
NumberBoostStates = 0;
} else {
PciAddress.AddressValue = CPB_CTRL_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &CpbCtrl, StdHeader); // D18F4x15C
NumberBoostStates = (UINT8) CpbCtrl.NumBoostStates;
}
// update PstateMaxVal if warranted by HtcPstateLimit
PciAddress.AddressValue = NB_CAPS_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &NbCaps, StdHeader);
if (NbCaps.HtcCapable == 1) {
if (HtcReg.HtcTmpLmt != 0) {
PciAddress.AddressValue = CPTC2_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &ClkPwrTimingCtrl2, StdHeader); // D18F3xDC
if (HtcReg.HtcPstateLimit > ClkPwrTimingCtrl2.PstateMaxVal) {
ClkPwrTimingCtrl2.PstateMaxVal = HtcReg.HtcPstateLimit;
LibAmdPciWrite (AccessWidth32, PciAddress, &ClkPwrTimingCtrl2, StdHeader); // D18F3xDC
}
}
}
DisHwPsNum = 0;
for (Pstate = 0; Pstate < ErrorData.HwPstateNumber; Pstate++) {
if (FamilySpecificServices->GetProcIddMax (FamilySpecificServices, Pstate, &ProcIddMax, StdHeader)) {
if (ProcIddMax > CpuEarlyParams->PlatformConfig.VrmProperties[CoreVrm].CurrentLimit) {
@ -190,17 +231,23 @@ F14PmPwrCheck (
PutEventLog (AGESA_WARNING,
CPU_EVENT_PM_PSTATE_OVERCURRENT,
Socket, Pstate, 0, 0, StdHeader);
DisPsNum++;
DisHwPsNum++;
} else {
break;
}
}
}
// get the number of software Pstate that is disabled by delivery check
if (NumberBoostStates < DisHwPsNum) {
DisSwPsNum = DisHwPsNum - NumberBoostStates;
} else {
DisSwPsNum = 0;
}
// If all P-state registers are disabled, move P[PsMaxVal] to P0
// and transition to P0, then wait for CurPstate = 0
ErrorData.AllowablePstateNumber = ((PsMaxVal + 1) - DisPsNum);
ErrorData.AllowablePstateNumber = ((PsMaxVal + 1) - DisHwPsNum);
// We only need to log this event on the BSC
if (ErrorData.AllowablePstateNumber == 0) {
@ -209,7 +256,15 @@ F14PmPwrCheck (
Socket, 0, 0, 0, StdHeader);
}
if (DisPsNum != 0) {
if (DisHwPsNum != 0) {
// Program F4x15C[BoostSrc] = 0
if ((CpuFamilyRevision.Revision & (AMD_F14_ON_Ax | AMD_F14_ON_Bx)) == 0) {
PciAddress.AddressValue = CPB_CTRL_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &CpbCtrl, StdHeader); // D18F4x15C
CpbCtrl.BoostSrc = 0;
LibAmdPciWrite (AccessWidth32, PciAddress, &CpbCtrl, StdHeader); // D18F4x15C
}
TaskPtr.FuncAddress.PfApTaskI = F14PmPwrCheckCore;
TaskPtr.DataTransfer.DataSizeInDwords = SIZE_IN_DWORDS (PWRCHK_ERROR_DATA);
TaskPtr.DataTransfer.DataPtr = &ErrorData;
@ -220,28 +275,32 @@ F14PmPwrCheck (
// Final Step
// D18F3x64[HtPstatelimit] -= disPsNum
// D18F3xDC[PstateMaxVal]-= disPsNum
PciAddress.AddressValue = HTC_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader); // D18F3x64
PstateLimit = ((HTC_REGISTER *) &PciRegister)->HtcPstateLimit;
if (PstateLimit > DisPsNum) {
PstateLimit -= DisPsNum;
LibAmdPciRead (AccessWidth32, PciAddress, &HtcReg, StdHeader); // D18F3x64
PciAddress.AddressValue = NB_CAPS_PCI_ADDR; // D18F3xE8
LibAmdPciRead (AccessWidth32, PciAddress, &NbCaps, StdHeader);
if (ThermalPstateEn || HtcReg.HtcTmpLmt == 0 || NbCaps.HtcCapable == 0) {
PstateLimit = (UINT8) HtcReg.HtcPstateLimit;
if (PstateLimit > DisHwPsNum) {
PstateLimit = (UINT8) (PstateLimit - DisSwPsNum);
} else {
PstateLimit = 0;
PstateLimit = NumberBoostStates;
}
((HTC_REGISTER *) &PciRegister)->HtcPstateLimit = PstateLimit;
LibAmdPciWrite (AccessWidth32, PciAddress, &PciRegister, StdHeader); // D18F3x64
HtcReg.HtcPstateLimit = PstateLimit;
PciAddress.AddressValue = HTC_PCI_ADDR;
LibAmdPciWrite (AccessWidth32, PciAddress, &HtcReg, StdHeader); // D18F3x64
PciAddress.AddressValue = CPTC2_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader); // D18F3xDC
PstateLimit = ((CLK_PWR_TIMING_CTRL2_REGISTER *) &PciRegister)->PstateMaxVal;
if (PstateLimit > DisPsNum) {
PstateLimit -= DisPsNum;
LibAmdPciRead (AccessWidth32, PciAddress, &ClkPwrTimingCtrl2, StdHeader); // D18F3xDC
PstateLimit = (UINT8) ClkPwrTimingCtrl2.PstateMaxVal;
if (PstateLimit > DisHwPsNum) {
PstateLimit = (UINT8) (PstateLimit - DisSwPsNum);
} else {
PstateLimit = 0;
PstateLimit = NumberBoostStates;
}
ClkPwrTimingCtrl2.PstateMaxVal = PstateLimit;
LibAmdPciWrite (AccessWidth32, PciAddress, &ClkPwrTimingCtrl2, StdHeader); // D18F3xDC
}
((CLK_PWR_TIMING_CTRL2_REGISTER *) &PciRegister)->PstateMaxVal = PstateLimit;
LibAmdPciWrite (AccessWidth32, PciAddress, &PciRegister, StdHeader); // D18F3xDC
}
}
@ -265,37 +324,64 @@ F14PmPwrCheckCore (
)
{
UINT8 i;
UINT8 PsMaxVal;
UINT8 DisPsNum;
UINT8 CurrentPs;
UINT64 MsrRegister;
UINT8 HardwarePsMaxVal;
UINT8 DisHwPsNum;
UINT8 DisSwPsNum;
UINT8 CurrentSoftwarePs;
UINT8 CurrentHardwarePs;
UINT8 NumberBoostStates;
UINT64 LocalMsrRegister;
CPU_LOGICAL_ID CpuFamilyRevision;
PCI_ADDR PciAddress;
CPB_CTRL_REGISTER CpbCtrl;
CPU_SPECIFIC_SERVICES *FamilySpecificServices;
GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader);
GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
GetLogicalIdOfCurrentCore (&CpuFamilyRevision, StdHeader);
PsMaxVal = (((PWRCHK_ERROR_DATA *) ErrorData)->HwPstateNumber - 1);
DisPsNum = (((PWRCHK_ERROR_DATA *) ErrorData)->HwPstateNumber -
HardwarePsMaxVal = (((PWRCHK_ERROR_DATA *) ErrorData)->HwPstateNumber - 1);
DisHwPsNum = (((PWRCHK_ERROR_DATA *) ErrorData)->HwPstateNumber -
((PWRCHK_ERROR_DATA *) ErrorData)->AllowablePstateNumber);
LibAmdMsrRead (MSR_PSTATE_STS, &MsrRegister, StdHeader);
CurrentPs = (UINT8) (((PSTATE_STS_MSR *) &MsrRegister)->CurPstate);
LibAmdMsrRead (MSR_PSTATE_STS, &LocalMsrRegister, StdHeader);
CurrentSoftwarePs = (UINT8) (((PSTATE_STS_MSR *) &LocalMsrRegister)->CurPstate);
if ((CpuFamilyRevision.Revision & (AMD_F14_ON_Ax | AMD_F14_ON_Bx)) != 0) {
NumberBoostStates = 0;
} else {
PciAddress.AddressValue = CPB_CTRL_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &CpbCtrl, StdHeader); // D18F4x15C
NumberBoostStates = (UINT8) CpbCtrl.NumBoostStates;
}
CurrentHardwarePs = CurrentSoftwarePs + NumberBoostStates;
if (NumberBoostStates < DisHwPsNum) {
DisSwPsNum = DisHwPsNum - NumberBoostStates;
} else {
DisSwPsNum = 0;
}
if (((PWRCHK_ERROR_DATA *) ErrorData)->AllowablePstateNumber == 0) {
// Step 1
// Transition to Pstate Max if not there already
if (CurrentPs != PsMaxVal) {
FamilySpecificServices->TransitionPstate (FamilySpecificServices, PsMaxVal, (BOOLEAN) TRUE, StdHeader);
if (CurrentHardwarePs != HardwarePsMaxVal) {
FamilySpecificServices->TransitionPstate (FamilySpecificServices, (HardwarePsMaxVal - NumberBoostStates), (BOOLEAN) TRUE, StdHeader);
CurrentSoftwarePs = HardwarePsMaxVal - NumberBoostStates;
}
// Step 2
// If Pstate Max is not P0, copy Pstate max contents to P0 and switch
// If CurrentSoftwarePs is not P0, copy CurrentSoftwarePs contents to Software P0 and switch
// to P0.
if (PsMaxVal != 0) {
F14PmPwrChkCopyPstate (0, PsMaxVal, StdHeader);
if (CurrentSoftwarePs != 0) {
F14PmPwrChkCopyPstate (NumberBoostStates, CurrentSoftwarePs, StdHeader);
LibAmdMsrRead ((PS_REG_BASE + NumberBoostStates), &LocalMsrRegister, StdHeader);
((PSTATE_MSR *) &LocalMsrRegister)->PsEnable = 1;
LibAmdMsrWrite ((PS_REG_BASE + NumberBoostStates), &LocalMsrRegister, StdHeader);
FamilySpecificServices->TransitionPstate (FamilySpecificServices, (UINT8) 0, (BOOLEAN) TRUE, StdHeader);
}
} else {
@ -304,29 +390,39 @@ F14PmPwrCheckCore (
// Step 1
// Transition to a valid Pstate if current Pstate has been disabled
if (CurrentPs < DisPsNum) {
FamilySpecificServices->TransitionPstate (FamilySpecificServices, DisPsNum, (BOOLEAN) TRUE, StdHeader);
CurrentPs = DisPsNum;
if (CurrentHardwarePs < DisHwPsNum) {
FamilySpecificServices->TransitionPstate (FamilySpecificServices, (HardwarePsMaxVal - NumberBoostStates), (BOOLEAN) TRUE, StdHeader);
CurrentSoftwarePs = HardwarePsMaxVal - NumberBoostStates;
}
if (DisSwPsNum != 0) {
// Step 2
// Move enabled Pstates up and disable the remainder
for (i = 0; (i + DisPsNum) <= PsMaxVal; ++i) {
F14PmPwrChkCopyPstate (i, (i + DisPsNum), StdHeader);
for (i = 0; (i + DisHwPsNum) <= HardwarePsMaxVal; ++i) {
F14PmPwrChkCopyPstate ((i + NumberBoostStates), (i + DisHwPsNum), StdHeader);
}
// Step 3
// Transition to current COF/VID at shifted location
CurrentPs = (CurrentPs - DisPsNum);
FamilySpecificServices->TransitionPstate (FamilySpecificServices, CurrentPs, (BOOLEAN) TRUE, StdHeader);
CurrentSoftwarePs = (CurrentSoftwarePs - DisSwPsNum);
FamilySpecificServices->TransitionPstate (FamilySpecificServices, CurrentSoftwarePs, (BOOLEAN) TRUE, StdHeader);
}
}
i = ((PWRCHK_ERROR_DATA *) ErrorData)->AllowablePstateNumber;
if (i == 0) {
i++;
if (((PWRCHK_ERROR_DATA *) ErrorData)->AllowablePstateNumber == 0) {
// only software P0 should be enabled.
i = NumberBoostStates + 1;
} else {
if (DisSwPsNum == 0) {
// No software Pstate is disabed, set i = HardwarePsMaxVal + 1 to skip below 'while loop'.
i = HardwarePsMaxVal + 1;
} else {
// get the first software Pstate that should be disabled.
i = HardwarePsMaxVal - DisSwPsNum + 1;
}
while (i <= PsMaxVal) {
}
while (i <= HardwarePsMaxVal) {
FamilySpecificServices->DisablePstate (FamilySpecificServices, i, StdHeader);
i++;
}
@ -350,9 +446,9 @@ F14PmPwrChkCopyPstate (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT64 MsrRegister;
UINT64 LocalMsrRegister;
LibAmdMsrRead ((UINT32) (PS_REG_BASE + Src), &MsrRegister, StdHeader);
LibAmdMsrWrite ((UINT32) (PS_REG_BASE + Dest), &MsrRegister, StdHeader);
LibAmdMsrRead ((UINT32) (PS_REG_BASE + Src), &LocalMsrRegister, StdHeader);
LibAmdMsrWrite ((UINT32) (PS_REG_BASE + Dest), &LocalMsrRegister, StdHeader);
}

73
src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14PowerMgmt.h
View File

@ -7,7 +7,7 @@
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/F14
* @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
* @e \$Revision: 46836 $ @e \$Date: 2011-02-10 12:22:59 -0700 (Thu, 10 Feb 2011) $
*
*/
/*
@ -110,6 +110,20 @@ typedef struct {
} PSTATE_MSR;
/* COFVID Control Register 0xC0010070 */
#define MSR_COFVID_CTL 0xC0010070
/// COFVID Control MSR Register
typedef struct {
UINT64 CpuDid:4; ///< CPU core divisor identifier
UINT64 CpuDidMSD:5; ///< CPU core frequency identifier
UINT64 CpuVid:7; ///< CPU core VID
UINT64 PstateId:3; ///< P-state identifier
UINT64 IgnoreFidVidDid:1; ///< Ignore FID, VID, and DID
UINT64 :44; ///< Reserved
} COFVID_CTRL_MSR;
/* COFVID Status Register 0xC0010071 */
#define MSR_COFVID_STS 0xC0010071
@ -301,6 +315,36 @@ typedef struct {
UINT32 :16; ///< Reserved
} CLK_PWR_TIMING_CTRL3_REGISTER;
/* Local hardware thermal control register D18F3x138 */
#define LHTC_REG 0x138
#define LHTC_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_3, LHTC_REG))
/// Local Hardware Thermal Control PCI Register
typedef struct {
UINT32 LHtcEn:1; ///< Local HTC Enable
UINT32 :7; ///< Reserved
UINT32 LHtcAct:2; ///< Local HTC Active State
UINT32 :2; ///< Reserved
UINT32 LHtcActSts:2; ///< Local HTC Active Status
UINT32 :2; ///< Reserved
UINT32 LHtcTmpLmt:7; ///< Local HTC temperature limit
UINT32 LHtcSlewSel:1; ///< Local HTC slew-controlled temp select
UINT32 LHtcHystLmt:4; ///< Local HTC hysteresis
UINT32 LHtcPstateLimit:3; ///< Local HTC P-state limit select
UINT32 LHtcLock:1; ///< HTC lock
} LHTC_REGISTER;
/* Product Information Register D18F3x1FC */
#define PRODUCT_INFO_REG 0x1FC
#define PRODUCT_INFO_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_3, PRODUCT_INFO_REG))
/// Product Information PCI Register
typedef struct {
UINT32 :2; ///< Reserved
UINT32 LowPowerDefault:1; ///< Low Power Default
UINT32 :29; ///< Reserved
} PRODUCT_INFO_REGISTER;
/* C-state Control 1 Register D18F4x118 */
#define CSTATE_CTRL1_REG 0x118
@ -336,6 +380,33 @@ typedef struct {
} CSTATE_CTRL2_REGISTER;
/* C-state Monitor Control 3 Register D18F4x134 */
#define CSTATE_MON_CTRL3_REG 0x134
#define CSTATE_MON_CTRL3_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_4, CSTATE_MON_CTRL3_REG))
/// C-state Monitor Control 3 Register
typedef struct {
UINT32 IntRatePkgC6MaxDepth:4; ///< Interrupt rate monitor PC6 maximum counter depth
UINT32 IntRatePkgC6Threshold:4; ///< Interrupt rate monitor PC6 threshold
UINT32 IntRatePkgC6BurstLen:3; ///< Interrupt rate monitor PC6 burst length
UINT32 IntRatePkgC6DecrRate:5; ///< Interrupt rate monitor PC6 decrement rate
UINT32 IntRateCC6MaxDepth:4; ///< Interrupt rate monitor CC6 maximum counter depth
UINT32 IntRateCC6Threshold:4; ///< Interrupt rate monitor CC6 threshold
UINT32 IntRateCC6BurstLen:3; ///< Interrupt rate monitor CC6 burst length
UINT32 IntRateCC6DecrRate:5; ///< Interrupt rate monitor CC6 decrement rate
} CSTATE_MON_CTRL3_REGISTER;
/* LPMV Scalar 2 Register D18F4x14C */
#define LPMV_SCALAR2_REG 0x14C
#define LPMV_SCALAR2_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_4, LPMV_SCALAR2_REG))
/// LPMV Scalar 2 Register
typedef struct {
UINT32 :24; ///< Reserved
UINT32 ApmCstExtPol:2; ///< Number of boosted states
UINT32 :6; ///< Reserved
} LPMV_SCALAR2_REGISTER;
/* Core Performance Boost Control Register D18F4x15C */
#define CPB_CTRL_REG 0x15C
#define CPB_CTRL_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_4, CPB_CTRL_REG))

20
src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14PowerMgmtSystemTables.c
View File

@ -7,7 +7,7 @@
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU
* @e \$Revision: 37018 $ @e \$Date: 2010-08-28 05:46:16 +0800 (Sat, 28 Aug 2010) $
* @e \$Revision: 45626 $ @e \$Date: 2011-01-19 09:58:02 -0700 (Wed, 19 Jan 2011) $
*
*/
/*
@ -55,6 +55,7 @@
#include "cpuF14SoftwareThermal.h"
#include "cpuF14PowerPlane.h"
#include "cpuF14PowerCheck.h"
#include "cpuF14LowPowerInit.h"
#include "Filecode.h"
#define FILECODE PROC_CPU_FAMILY_0X14_CPUF14POWERMGMTSYSTEMTABLES_FILECODE
@ -73,6 +74,14 @@
*----------------------------------------------------------------------------------------
*/
VOID
GetF14SysPmTable (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
OUT CONST VOID **SysPmTblPtr,
OUT UINT8 *NumberOfElements,
IN AMD_CONFIG_PARAMS *StdHeader
);
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
@ -91,6 +100,13 @@ CONST SYS_PM_TBL_STEP ROMDATA CpuF14SysPmTableArray[] =
F14PmPwrPlaneInit // Function Pointer
},
// Step x - Optimizations for lower power
// Execute both cold & warm
{
0, // ExeFlags
F14OptimizeForLowPowerInit // Function Pointer
},
// Step 2 - Current Delivery Check
// Execute both cold & warm
{
@ -103,7 +119,7 @@ CONST SYS_PM_TBL_STEP ROMDATA CpuF14SysPmTableArray[] =
{
0, // ExeFlags
F14PmThermalInit // Function Pointer
},
}
};

41
src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14PowerPlane.c
View File

@ -57,6 +57,7 @@
#include "cpuFamilyTranslation.h"
#include "cpuServices.h"
#include "cpuF14PowerMgmt.h"
#include "cpuF14PowerPlane.h"
#include "OptionFamily14hEarlySample.h"
#include "NbSmuLib.h"
#include "GnbRegistersON.h"
@ -129,7 +130,7 @@ F14PmPwrPlaneInit (
)
{
UINT32 SystemSlewRate;
UINT32 PciRegister;
UINT32 PciReg;
UINT32 WaitTime;
UINT32 VSRampSlamTime;
PCI_ADDR PciAddress;
@ -166,9 +167,9 @@ F14PmPwrPlaneInit (
// Lastly, program D18F3xD8[VSRampSlamTime] with the appropriate encoded value.
PciAddress.AddressValue = CPTC1_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
((CLK_PWR_TIMING_CTRL1_REGISTER *) &PciRegister)->VSRampSlamTime = VSRampSlamTime;
LibAmdPciWrite (AccessWidth32, PciAddress, &PciRegister, StdHeader);
LibAmdPciRead (AccessWidth32, PciAddress, &PciReg, StdHeader);
((CLK_PWR_TIMING_CTRL1_REGISTER *) &PciReg)->VSRampSlamTime = VSRampSlamTime;
LibAmdPciWrite (AccessWidth32, PciAddress, &PciReg, StdHeader);
// Step 2 - Configure D18F3xA0[PsiVidEn & PsiVid] and D18F3x128[NbPsiVidEn & NbPsiVid].
F14PmVrmLowPowerModeEnable (FamilySpecificServices, CpuEarlyParams, StdHeader);
@ -180,11 +181,11 @@ F14PmPwrPlaneInit (
F14EarlySampleCoreSupport.F14PowerPlaneInitHook (&FCRxFE00_6000, StdHeader);
PciAddress.AddressValue = CPTC2_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
((CLK_PWR_TIMING_CTRL2_REGISTER *) &PciRegister)->NbPs0Vid = FCRxFE00_6000.Field.NbPs0Vid - 1;
LibAmdPciWrite (AccessWidth32, PciAddress, &PciRegister, StdHeader);
((CLK_PWR_TIMING_CTRL2_REGISTER *) &PciRegister)->NbPs0Vid = FCRxFE00_6000.Field.NbPs0Vid;
LibAmdPciWrite (AccessWidth32, PciAddress, &PciRegister, StdHeader);
LibAmdPciRead (AccessWidth32, PciAddress, &PciReg, StdHeader);
((CLK_PWR_TIMING_CTRL2_REGISTER *) &PciReg)->NbPs0Vid = FCRxFE00_6000.Field.NbPs0Vid - 1;
LibAmdPciWrite (AccessWidth32, PciAddress, &PciReg, StdHeader);
((CLK_PWR_TIMING_CTRL2_REGISTER *) &PciReg)->NbPs0Vid = FCRxFE00_6000.Field.NbPs0Vid;
LibAmdPciWrite (AccessWidth32, PciAddress, &PciReg, StdHeader);
}
/*---------------------------------------------------------------------------------------*/
@ -211,7 +212,7 @@ F14PmVrmLowPowerModeEnable (
UINT32 PstateCurrent;
UINT32 NextPstateCurrent;
UINT32 NextPstateCurrentRaw;
UINT32 PciRegister;
UINT32 PciReg;
UINT32 PreviousVid;
UINT32 CurrentVid;
UINT64 PstateMsr;
@ -249,24 +250,24 @@ F14PmVrmLowPowerModeEnable (
}
}
PciAddress.AddressValue = PW_CTL_MISC_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
LibAmdPciRead (AccessWidth32, PciAddress, &PciReg, StdHeader);
if (IsPsiEnabled) {
((POWER_CTRL_MISC_REGISTER *) &PciRegister)->PsiVid = CurrentVid;
((POWER_CTRL_MISC_REGISTER *) &PciRegister)->PsiVidEn = 1;
((POWER_CTRL_MISC_REGISTER *) &PciReg)->PsiVid = CurrentVid;
((POWER_CTRL_MISC_REGISTER *) &PciReg)->PsiVidEn = 1;
} else {
((POWER_CTRL_MISC_REGISTER *) &PciRegister)->PsiVidEn = 0;
((POWER_CTRL_MISC_REGISTER *) &PciReg)->PsiVidEn = 0;
}
LibAmdPciWrite (AccessWidth32, PciAddress, &PciRegister, StdHeader);
LibAmdPciWrite (AccessWidth32, PciAddress, &PciReg, StdHeader);
// Set up NBPSI_L for VDDNB
PciAddress.AddressValue = CPTC3_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
LibAmdPciRead (AccessWidth32, PciAddress, &PciReg, StdHeader);
if (CpuEarlyParams->PlatformConfig.VrmProperties[NbVrm].LowPowerThreshold != 0) {
((CLK_PWR_TIMING_CTRL3_REGISTER *) &PciRegister)->NbPsiVid = 0;
((CLK_PWR_TIMING_CTRL3_REGISTER *) &PciRegister)->NbPsiVidEn = 1;
((CLK_PWR_TIMING_CTRL3_REGISTER *) &PciReg)->NbPsiVid = 0;
((CLK_PWR_TIMING_CTRL3_REGISTER *) &PciReg)->NbPsiVidEn = 1;
} else {
((CLK_PWR_TIMING_CTRL3_REGISTER *) &PciRegister)->NbPsiVidEn = 0;
((CLK_PWR_TIMING_CTRL3_REGISTER *) &PciReg)->NbPsiVidEn = 0;
}
LibAmdPciWrite (AccessWidth32, PciAddress, &PciRegister, StdHeader);
LibAmdPciWrite (AccessWidth32, PciAddress, &PciReg, StdHeader);
}

114
src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14Pstate.c
View File

@ -9,7 +9,7 @@
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/F14
* @e \$Revision: 37010 $ @e \$Date: 2010-08-28 03:10:12 +0800 (Sat, 28 Aug 2010) $
* @e \$Revision: 44325 $ @e \$Date: 2010-12-22 03:29:53 -0700 (Wed, 22 Dec 2010) $
*
*/
/*
@ -75,6 +75,49 @@
*----------------------------------------------------------------------------------------
*/
AGESA_STATUS
F14GetPstateTransLatency (
IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices,
IN PSTATE_LEVELING *PStateLevelingBufferStructPtr,
IN PCI_ADDR *PciAddress,
OUT UINT32 *TransitionLatency,
IN AMD_CONFIG_PARAMS *StdHeader
);
AGESA_STATUS
F14GetPstateFrequency (
IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices,
IN UINT8 StateNumber,
OUT UINT32 *FrequencyInMHz,
IN AMD_CONFIG_PARAMS *StdHeader
);
AGESA_STATUS
F14GetPstatePower (
IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices,
IN UINT8 StateNumber,
OUT UINT32 *PowerInMw,
IN AMD_CONFIG_PARAMS *StdHeader
);
AGESA_STATUS
F14GetPstateMaxState (
IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices,
OUT UINT32 *MaxPStateNumber,
IN AMD_CONFIG_PARAMS *StdHeader
);
AGESA_STATUS
F14GetPstateRegisterInfo (
IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices,
IN UINT32 PState,
OUT BOOLEAN *PStateEnabled,
IN OUT UINT32 *IddVal,
IN OUT UINT32 *IddDiv,
OUT UINT32 *SwPstateNumber,
IN AMD_CONFIG_PARAMS *StdHeader
);
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
@ -154,8 +197,8 @@ F14GetPstateFrequency (
UINT32 CpuDidLSD;
UINT32 CpuDidMSD;
UINT32 CoreClkDivisor;
UINT32 PciRegister;
UINT64 MsrRegister;
UINT32 PciReg;
UINT64 MsrReg;
BOOLEAN FrequencyCalculated;
BOOLEAN ClockDivisorCalculated;
PCI_ADDR PciAddress;
@ -164,11 +207,11 @@ F14GetPstateFrequency (
ASSERT (StateNumber < NM_PS_REG);
LibAmdMsrRead (PS_REG_BASE + (UINT32) StateNumber, &MsrRegister, StdHeader);
ASSERT (((PSTATE_MSR *) &MsrRegister)->PsEnable == 1);
LibAmdMsrRead (PS_REG_BASE + (UINT32) StateNumber, &MsrReg, StdHeader);
ASSERT (((PSTATE_MSR *) &MsrReg)->PsEnable == 1);
CpuDidLSD = (UINT32) (((PSTATE_MSR *) &MsrRegister)->CpuDidLSD);
CpuDidMSD = (UINT32) (((PSTATE_MSR *) &MsrRegister)->CpuDidMSD);
CpuDidLSD = (UINT32) (((PSTATE_MSR *) &MsrReg)->CpuDidLSD);
CpuDidMSD = (UINT32) (((PSTATE_MSR *) &MsrReg)->CpuDidMSD);
FrequencyCalculated = FALSE;
ClockDivisorCalculated = FALSE;
@ -194,10 +237,10 @@ F14GetPstateFrequency (
if (!FrequencyCalculated) {
// Get D18F3xD4[MainPllOpFreqId] frequency
PciAddress.AddressValue = CPTC0_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
LibAmdPciRead (AccessWidth32, PciAddress, &PciReg, StdHeader);
if (((CLK_PWR_TIMING_CTRL_REGISTER *) &PciRegister)->MainPllOpFreqIdEn == 1) {
MainPllFid = ((CLK_PWR_TIMING_CTRL_REGISTER *) &PciRegister)->MainPllOpFreqId;
if (((CLK_PWR_TIMING_CTRL_REGISTER *) &PciReg)->MainPllOpFreqIdEn == 1) {
MainPllFid = ((CLK_PWR_TIMING_CTRL_REGISTER *) &PciReg)->MainPllOpFreqId;
} else {
MainPllFid = 0;
}
@ -234,14 +277,14 @@ F14GetPstatePower (
UINT32 IddDiv;
UINT32 V_x10000;
UINT32 Power;
UINT64 MsrRegister;
UINT64 MsrReg;
ASSERT (StateNumber < NM_PS_REG);
LibAmdMsrRead (PS_REG_BASE + (UINT32) StateNumber, &MsrRegister, StdHeader);
ASSERT (((PSTATE_MSR *) &MsrRegister)->PsEnable == 1);
CpuVid = (UINT32) (((PSTATE_MSR *) &MsrRegister)->CpuVid);
IddValue = (UINT32) (((PSTATE_MSR *) &MsrRegister)->IddValue);
IddDiv = (UINT32) (((PSTATE_MSR *) &MsrRegister)->IddDiv);
LibAmdMsrRead (PS_REG_BASE + (UINT32) StateNumber, &MsrReg, StdHeader);
ASSERT (((PSTATE_MSR *) &MsrReg)->PsEnable == 1);
CpuVid = (UINT32) (((PSTATE_MSR *) &MsrReg)->CpuVid);
IddValue = (UINT32) (((PSTATE_MSR *) &MsrReg)->IddValue);
IddDiv = (UINT32) (((PSTATE_MSR *) &MsrReg)->IddDiv);
if (CpuVid >= 0x7C) {
V_x10000 = 0;
@ -289,13 +332,19 @@ F14GetPstateMaxState (
)
{
UINT64 MsrValue;
UINT32 PciReg;
PCI_ADDR PciAddress;
// For F14 CPU, skip boosted p-state. The boosted p-state number = D18F4x15C[NumBoostStates].
PciAddress.AddressValue = CPB_CTRL_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &PciReg, StdHeader); // D18F4x15C
//
// Read PstateMaxVal [6:4] from MSR C001_0061
// So, we will know the max pstate state in this socket.
//
LibAmdMsrRead (MSR_PSTATE_CURRENT_LIMIT, &MsrValue, StdHeader);
*MaxPStateNumber = (UINT32) (((PSTATE_CURLIM_MSR *) &MsrValue)->PstateMaxVal);
*MaxPStateNumber = (UINT32) (((PSTATE_CURLIM_MSR *) &MsrValue)->PstateMaxVal) + (UINT32) (((CPB_CTRL_REGISTER *) &PciReg)->NumBoostStates);
return (AGESA_SUCCESS);
}
@ -325,25 +374,44 @@ F14GetPstateRegisterInfo (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT64 MsrRegister;
UINT64 LocalMsrReg;
UINT32 LocalPciReg;
PCI_ADDR PciAddress;
CPU_LOGICAL_ID CpuFamilyRevision;
ASSERT (PState < NM_PS_REG);
// Read PSTATE MSRs
LibAmdMsrRead (PS_REG_BASE + (UINT32) PState, &MsrRegister, StdHeader);
LibAmdMsrRead (PS_REG_BASE + (UINT32) PState, &LocalMsrReg, StdHeader);
if (((PSTATE_MSR *) &MsrRegister)->PsEnable == 1) {
*SwPstateNumber = PState;
if (((PSTATE_MSR *) &LocalMsrReg)->PsEnable == 1) {
// PState enable = bit 63
*PStateEnabled = TRUE;
// For F14 CPU, skip boosted p-state. The boosted p-state number = D18F4x15C[NumBoostStates].
GetLogicalIdOfCurrentCore (&CpuFamilyRevision, StdHeader);
if ((CpuFamilyRevision.Revision & (AMD_F14_ON_Ax | AMD_F14_ON_Bx)) == 0) {
// ON_Ax & ON_Bx don't have boosted p-state function
PciAddress.AddressValue = CPB_CTRL_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciReg, StdHeader); // D18F4x15C
//
// Check input pstate belongs to Boosted-Pstate, if yes, return *PStateEnabled = FALSE.
//
if (PState < ((CPB_CTRL_REGISTER *) &LocalPciReg)->NumBoostStates) {
*PStateEnabled = FALSE;
} else {
*SwPstateNumber = PState - ((CPB_CTRL_REGISTER *) &LocalPciReg)->NumBoostStates;
}
}
} else {
*PStateEnabled = FALSE;
}
*SwPstateNumber = PState;
// Bits 39:32 (high 32 bits [7:0])
*IddVal = (UINT32) ((PSTATE_MSR *) &MsrRegister)->IddValue;
*IddVal = (UINT32) ((PSTATE_MSR *) &LocalMsrReg)->IddValue;
// Bits 41:40 (high 32 bits [9:8])
*IddDiv = (UINT32) ((PSTATE_MSR *) &MsrRegister)->IddDiv;
*IddDiv = (UINT32) ((PSTATE_MSR *) &LocalMsrReg)->IddDiv;
return (AGESA_SUCCESS);
}

33
src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14SoftwareThermal.c
View File

@ -9,7 +9,7 @@
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/F14
* @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
* @e \$Revision: 46836 $ @e \$Date: 2011-02-10 12:22:59 -0700 (Thu, 10 Feb 2011) $
*
*/
/*
@ -50,10 +50,10 @@
*/
#include "AGESA.h"
#include "amdlib.h"
#include "cpuCacheInit.h"
#include "cpuRegisters.h"
#include "cpuFamilyTranslation.h"
#include "cpuF14PowerMgmt.h"
#include "cpuF14SoftwareThermal.h"
#include "Filecode.h"
#define FILECODE PROC_CPU_FAMILY_0X14_CPUF14SOFTWARETHERMAL_FILECODE
@ -95,18 +95,33 @@ F14PmThermalInit (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 PciRegister;
UINT32 NbCaps;
UINT32 LocalPciRegister;
PCI_ADDR PciAddress;
CPU_LOGICAL_ID CpuFamilyRevision;
PciAddress.AddressValue = NB_CAPS_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
if (((NB_CAPS_REGISTER *) &PciRegister)->HtcCapable == 1) {
LibAmdPciRead (AccessWidth32, PciAddress, &NbCaps, StdHeader);
if (((NB_CAPS_REGISTER *) &NbCaps)->HtcCapable == 1) {
PciAddress.AddressValue = HTC_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
if (((HTC_REGISTER *) &PciRegister)->HtcTmpLmt != 0) {
LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
if (((HTC_REGISTER *) &LocalPciRegister)->HtcTmpLmt != 0) {
// Enable HTC
((HTC_REGISTER *) &PciRegister)->HtcEn = 1;
LibAmdPciWrite (AccessWidth32, PciAddress, &PciRegister, StdHeader);
((HTC_REGISTER *) &LocalPciRegister)->HtcEn = 1;
LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
}
}
GetLogicalIdOfCurrentCore (&CpuFamilyRevision, StdHeader);
if ((CpuFamilyRevision.Revision & AMD_F14_ON_Cx) != 0) {
PciAddress.AddressValue = LHTC_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
if (((NB_CAPS_REGISTER *) &NbCaps)->LHtcCapable == 1) {
if (((LHTC_REGISTER *) &LocalPciRegister)->LHtcTmpLmt != 0) {
// Enable local HTC
((LHTC_REGISTER *) &LocalPciRegister)->LHtcEn = 1;
}
}
LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
}
}

108
src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14Utilities.c
View File

@ -84,6 +84,38 @@ F14ConvertEnabledBitsIntoCount (
IN UINT8 EnabledCores
);
BOOLEAN
F14GetNbPstateInfo (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN PLATFORM_CONFIGURATION *PlatformConfig,
IN PCI_ADDR *PciAddress,
IN UINT32 NbPstate,
OUT UINT32 *FreqNumeratorInMHz,
OUT UINT32 *FreqDivisor,
OUT UINT32 *VoltageInuV,
IN AMD_CONFIG_PARAMS *StdHeader
);
BOOLEAN
F14IsNbPstateEnabled (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN PLATFORM_CONFIGURATION *PlatformConfig,
IN AMD_CONFIG_PARAMS *StdHeader
);
BOOLEAN
F14GetProcIddMax (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN UINT8 Pstate,
OUT UINT32 *ProcIddMax,
IN AMD_CONFIG_PARAMS *StdHeader
);
UINT8
F14GetNumberOfCoresForBrandstring (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN AMD_CONFIG_PARAMS *StdHeader
);
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
@ -132,12 +164,12 @@ F14DisablePstate (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT64 MsrRegister;
UINT64 MsrReg;
ASSERT (StateNumber < NM_PS_REG);
LibAmdMsrRead (PS_REG_BASE + (UINT32) StateNumber, &MsrRegister, StdHeader);
((PSTATE_MSR *) &MsrRegister)->PsEnable = 0;
LibAmdMsrWrite (PS_REG_BASE + (UINT32) StateNumber, &MsrRegister, StdHeader);
LibAmdMsrRead (PS_REG_BASE + (UINT32) StateNumber, &MsrReg, StdHeader);
((PSTATE_MSR *) &MsrReg)->PsEnable = 0;
LibAmdMsrWrite (PS_REG_BASE + (UINT32) StateNumber, &MsrReg, StdHeader);
return (AGESA_SUCCESS);
}
@ -162,18 +194,18 @@ F14TransitionPstate (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT64 MsrRegister;
UINT64 MsrReg;
ASSERT (StateNumber < NM_PS_REG);
LibAmdMsrRead (PS_REG_BASE + (UINT32) StateNumber, &MsrRegister, StdHeader);
ASSERT (((PSTATE_MSR *) &MsrRegister)->PsEnable == 1);
LibAmdMsrRead (MSR_PSTATE_CTL, &MsrRegister, StdHeader);
((PSTATE_CTRL_MSR *) &MsrRegister)->PstateCmd = (UINT64) StateNumber;
LibAmdMsrWrite (MSR_PSTATE_CTL, &MsrRegister, StdHeader);
LibAmdMsrRead (PS_REG_BASE + (UINT32) StateNumber, &MsrReg, StdHeader);
ASSERT (((PSTATE_MSR *) &MsrReg)->PsEnable == 1);
LibAmdMsrRead (MSR_PSTATE_CTL, &MsrReg, StdHeader);
((PSTATE_CTRL_MSR *) &MsrReg)->PstateCmd = (UINT64) StateNumber;
LibAmdMsrWrite (MSR_PSTATE_CTL, &MsrReg, StdHeader);
if (WaitForTransition) {
do {
LibAmdMsrRead (MSR_PSTATE_STS, &MsrRegister, StdHeader);
} while (((PSTATE_STS_MSR *) &MsrRegister)->CurPstate != (UINT64) StateNumber);
LibAmdMsrRead (MSR_PSTATE_STS, &MsrReg, StdHeader);
} while (((PSTATE_STS_MSR *) &MsrReg)->CurPstate != (UINT64) StateNumber);
}
return (AGESA_SUCCESS);
}
@ -198,15 +230,15 @@ F14GetTscRate (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT64 MsrRegister;
UINT64 MsrReg;
PSTATE_CPU_FAMILY_SERVICES *FamilyServices;
FamilyServices = NULL;
GetFeatureServicesOfCurrentCore (&PstateFamilyServiceTable, &FamilyServices, StdHeader);
GetFeatureServicesOfCurrentCore (&PstateFamilyServiceTable, (const VOID **)&FamilyServices, StdHeader);
ASSERT (FamilyServices != NULL);
LibAmdMsrRead (0xC0010015, &MsrRegister, StdHeader);
if ((MsrRegister & 0x01000000) != 0) {
LibAmdMsrRead (0xC0010015, &MsrReg, StdHeader);
if ((MsrReg & 0x01000000) != 0) {
return (FamilyServices->GetPstateFrequency (FamilyServices, 0, FrequencyInMHz, StdHeader));
} else {
return (FamilySpecificServices->GetCurrentNbFrequency (FamilySpecificServices, FrequencyInMHz, StdHeader));
@ -232,15 +264,15 @@ F14GetCurrentNbFrequency (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 PciRegister;
UINT32 PciReg;
UINT32 MainPllFid;
PCI_ADDR PciAddress;
PciAddress.AddressValue = CPTC0_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
LibAmdPciRead (AccessWidth32, PciAddress, &PciReg, StdHeader);
if (((CLK_PWR_TIMING_CTRL_REGISTER *) &PciRegister)->MainPllOpFreqIdEn == 1) {
MainPllFid = ((CLK_PWR_TIMING_CTRL_REGISTER *) &PciRegister)->MainPllOpFreqId;
if (((CLK_PWR_TIMING_CTRL_REGISTER *) &PciReg)->MainPllOpFreqIdEn == 1) {
MainPllFid = ((CLK_PWR_TIMING_CTRL_REGISTER *) &PciReg)->MainPllOpFreqId;
} else {
MainPllFid = 0;
}
@ -283,7 +315,7 @@ F14GetNbPstateInfo (
)
{
UINT32 NbVid;
UINT32 PciRegister;
UINT32 PciReg;
UINT32 MainPllFreq;
BOOLEAN PstateIsValid;
@ -294,15 +326,15 @@ F14GetNbPstateInfo (
if (NbPstate == 0) {
PciAddress->Address.Function = FUNC_3;
PciAddress->Address.Register = CPTC2_REG;
LibAmdPciRead (AccessWidth32, *PciAddress, &PciRegister, StdHeader);
*FreqDivisor = ((CLK_PWR_TIMING_CTRL2_REGISTER *) &PciRegister)->NbPs0NclkDiv;
NbVid = ((CLK_PWR_TIMING_CTRL2_REGISTER *) &PciRegister)->NbPs0Vid;
LibAmdPciRead (AccessWidth32, *PciAddress, &PciReg, StdHeader);
*FreqDivisor = ((CLK_PWR_TIMING_CTRL2_REGISTER *) &PciReg)->NbPs0NclkDiv;
NbVid = ((CLK_PWR_TIMING_CTRL2_REGISTER *) &PciReg)->NbPs0Vid;
} else {
PciAddress->Address.Function = FUNC_6;
PciAddress->Address.Register = NB_PSTATE_CFG_LOW_REG;
LibAmdPciRead (AccessWidth32, *PciAddress, &PciRegister, StdHeader);
*FreqDivisor = ((NB_PSTATE_CFG_LOW_REGISTER *) &PciRegister)->NbPs1NclkDiv;
NbVid = ((NB_PSTATE_CFG_LOW_REGISTER *) &PciRegister)->NbPs1Vid;
LibAmdPciRead (AccessWidth32, *PciAddress, &PciReg, StdHeader);
*FreqDivisor = ((NB_PSTATE_CFG_LOW_REGISTER *) &PciReg)->NbPs1NclkDiv;
NbVid = ((NB_PSTATE_CFG_LOW_REGISTER *) &PciReg)->NbPs1Vid;
}
*VoltageInuV = (1550000 - (12500 * NbVid));
PstateIsValid = TRUE;
@ -330,12 +362,12 @@ F14IsNbPstateEnabled (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 PciRegister;
UINT32 PciReg;
PCI_ADDR PciAddress;
PciAddress.AddressValue = NB_PSTATE_CFG_LOW_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
return ((BOOLEAN) (((NB_PSTATE_CFG_LOW_REGISTER *) &PciRegister)->NbPsCap == 1));
LibAmdPciRead (AccessWidth32, PciAddress, &PciReg, StdHeader);
return ((BOOLEAN) (((NB_PSTATE_CFG_LOW_REGISTER *) &PciReg)->NbPsCap == 1));
}
/*---------------------------------------------------------------------------------------*/
@ -391,7 +423,7 @@ F14LaunchApCore (
)
{
UINT32 NodeRelativeCoreNum;
UINT32 PciRegister;
UINT32 PciReg;
PCI_ADDR PciAddress;
BOOLEAN LaunchFlag;
@ -403,10 +435,10 @@ F14LaunchApCore (
switch (NodeRelativeCoreNum) {
case 1:
PciAddress.Address.Register = HT_TRANS_CTRL;
LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
if ((PciRegister & HT_TRANS_CTRL_CPU1_EN) == 0) {
PciRegister |= HT_TRANS_CTRL_CPU1_EN;
LibAmdPciWrite (AccessWidth32, PciAddress, &PciRegister, StdHeader);
LibAmdPciRead (AccessWidth32, PciAddress, &PciReg, StdHeader);
if ((PciReg & HT_TRANS_CTRL_CPU1_EN) == 0) {
PciReg |= HT_TRANS_CTRL_CPU1_EN;
LibAmdPciWrite (AccessWidth32, PciAddress, &PciReg, StdHeader);
LaunchFlag = TRUE;
} else {
LaunchFlag = FALSE;
@ -471,7 +503,7 @@ F14GetProcIddMax (
{
UINT32 IddDiv;
UINT32 CmpCap;
UINT32 PciRegister;
UINT32 PciReg;
UINT32 MsrAddress;
UINT64 PstateMsr;
BOOLEAN IsPstateEnabled;
@ -486,8 +518,8 @@ F14GetProcIddMax (
LibAmdMsrRead (MsrAddress, &PstateMsr, StdHeader);
if (((PSTATE_MSR *) &PstateMsr)->PsEnable == 1) {
PciAddress.AddressValue = NB_CAPS_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader); // F3xE8
CmpCap = (UINT32) (((NB_CAPS_REGISTER *) &PciRegister)->CmpCap);
LibAmdPciRead (AccessWidth32, PciAddress, &PciReg, StdHeader); // F3xE8
CmpCap = (UINT32) (((NB_CAPS_REGISTER *) &PciReg)->CmpCap);
CmpCap++;
switch (((PSTATE_MSR *) &PstateMsr)->IddDiv) {

8
src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14WheaInitDataTables.c
View File

@ -67,6 +67,14 @@
*----------------------------------------------------------------------------------------
*/
VOID
GetF14WheaInitData (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
OUT CONST VOID **F14WheaInitDataPtr,
OUT UINT8 *NumberOfElements,
IN AMD_CONFIG_PARAMS *StdHeader
);
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------

93
src/vendorcode/amd/agesa/f14/Proc/CPU/Family/cpuFamRegisters.h
View File

@ -70,37 +70,37 @@
// CPU_LOGICAL_ID.Family equates
// Family 10h equates
#define AMD_FAMILY_10_RB 0x0000000000000001
#define AMD_FAMILY_10_BL 0x0000000000000002
#define AMD_FAMILY_10_DA 0x0000000000000004
#define AMD_FAMILY_10_HY 0x0000000000000008
#define AMD_FAMILY_10_PH 0x0000000000000010
#define AMD_FAMILY_10_RB 0x0000000000000001ull
#define AMD_FAMILY_10_BL 0x0000000000000002ull
#define AMD_FAMILY_10_DA 0x0000000000000004ull
#define AMD_FAMILY_10_HY 0x0000000000000008ull
#define AMD_FAMILY_10_PH 0x0000000000000010ull
#define AMD_FAMILY_10_C32 AMD_FAMILY_10_HY
#define AMD_FAMILY_10 (AMD_FAMILY_10_RB | AMD_FAMILY_10_BL | AMD_FAMILY_10_DA | AMD_FAMILY_10_HY | AMD_FAMILY_10_PH)
#define AMD_FAMILY_GH (AMD_FAMILY_10)
// Family 12h equates
#define AMD_FAMILY_12_LN 0x0000000000000020
#define AMD_FAMILY_12_LN 0x0000000000000020ull
#define AMD_FAMILY_12 (AMD_FAMILY_12_LN)
#define AMD_FAMILY_LN (AMD_FAMILY_12_LN)
// Family 14h equates
#define AMD_FAMILY_14_ON 0x0000000000000040
#define AMD_FAMILY_14_ON 0x0000000000000040ull
#define AMD_FAMILY_14 (AMD_FAMILY_14_ON)
#define AMD_FAMILY_ON (AMD_FAMILY_14_ON)
// Family 15h equates
#define AMD_FAMILY_15_OR 0x0000000000000080
#define AMD_FAMILY_15_OR 0x0000000000000100ull
#define AMD_FAMILY_15 (AMD_FAMILY_15_OR)
#define AMD_FAMILY_OR (AMD_FAMILY_15_OR)
// Family 16h equates
#define AMD_FAMILY_16 0x0000000000000100
#define AMD_FAMILY_WF (AMD_FAMILY_16)
#define AMD_FAMILY_16 0x0000000000000800ull
#define AMD_FAMILY_WF (AMD_FAMILY_16)
// Family Unknown
#define AMD_FAMILY_UNKNOWN 0x8000000000000000
#define AMD_FAMILY_UNKNOWN 0x8000000000000000ull
// Family Group equates
#define AMD_FAMILY_GE_12 (AMD_FAMILY_12 | AMD_FAMILY_14 | AMD_FAMILY_15 | AMD_FAMILY_16)
@ -108,27 +108,27 @@
// Family 10h CPU_LOGICAL_ID.Revision equates
// -------------------------------------
// Family 10h RB steppings
#define AMD_F10_RB_C0 0x0000000000000001
#define AMD_F10_RB_C1 0x0000000000000002
#define AMD_F10_RB_C2 0x0000000000000004
#define AMD_F10_RB_C3 0x0000000000000008
#define AMD_F10_RB_C0 0x0000000000000001ull
#define AMD_F10_RB_C1 0x0000000000000002ull
#define AMD_F10_RB_C2 0x0000000000000004ull
#define AMD_F10_RB_C3 0x0000000000000008ull
// Family 10h BL steppings
#define AMD_F10_BL_C2 0x0000000000000010
#define AMD_F10_BL_C3 0x0000000000000020
#define AMD_F10_BL_C2 0x0000000000000010ull
#define AMD_F10_BL_C3 0x0000000000000020ull
// Family 10h DA steppings
#define AMD_F10_DA_C2 0x0000000000000040
#define AMD_F10_DA_C3 0x0000000000000080
#define AMD_F10_DA_C2 0x0000000000000040ull
#define AMD_F10_DA_C3 0x0000000000000080ull
// Family 10h HY SCM steppings
#define AMD_F10_HY_SCM_D0 0x0000000000000100
#define AMD_F10_HY_SCM_D1 0x0000000000000400
#define AMD_F10_HY_SCM_D0 0x0000000000000100ull
#define AMD_F10_HY_SCM_D1 0x0000000000000400ull
// Family 10h HY MCM steppings
#define AMD_F10_HY_MCM_D0 0x0000000000000200
#define AMD_F10_HY_MCM_D1 0x0000000000000800
#define AMD_F10_HY_MCM_D0 0x0000000000000200ull
#define AMD_F10_HY_MCM_D1 0x0000000000000800ull
// Family 10h PH steppings
#define AMD_F10_PH_E0 0x0000000000001000
#define AMD_F10_PH_E0 0x0000000000001000ull
// Family 10h Unknown stepping
#define AMD_F10_UNKNOWN 0x8000000000000000
#define AMD_F10_UNKNOWN 0x8000000000000000ull
// Family 10h Miscellaneous equates
#define AMD_F10_C0 (AMD_F10_RB_C0)
@ -168,43 +168,58 @@
// -------------------------------------
// Family 12h LN steppings
#define AMD_F12_LN_A0 0x0000000000000001
#define AMD_F12_LN_A1 0x0000000000000002
#define AMD_F12_LN_B0 0x0000000000000004
#define AMD_F12_LN_A0 0x0000000000000001ull
#define AMD_F12_LN_A1 0x0000000000000002ull
#define AMD_F12_LN_B0 0x0000000000000004ull
// Family 12h Unknown stepping
#define AMD_F12_UNKNOWN 0x8000000000000000
#define AMD_F12_UNKNOWN 0x8000000000000000ull
#define AMD_F12_LN_Ax (AMD_F12_LN_A0 | AMD_F12_LN_A1)
#define AMD_F12_LN_Bx (AMD_F12_LN_B0)
#define AMD_F12_ALL (AMD_F12_LN_Ax | AMD_F12_LN_Bx | AMD_F12_UNKNOWN)
#define AMD_F12_ALL (AMD_F12_LN_Ax | AMD_F12_LN_Bx | AMD_F12_UNKNOWN)
// Family 14h CPU_LOGICAL_ID.Revision equates
// -------------------------------------
// Family 14h ON steppings
#define AMD_F14_ON_A0 0x0000000000000001
#define AMD_F14_ON_A1 0x0000000000000002
#define AMD_F14_ON_B0 0x0000000000000004
#define AMD_F14_ON_A0 0x0000000000000001ull
#define AMD_F14_ON_A1 0x0000000000000002ull
#define AMD_F14_ON_B0 0x0000000000000004ull
#define AMD_F14_ON_C0 0x0000000000000008ull
// Family 14h KR steppings
#define AMD_F14_KR_A0 0x0000000000000100ull
#define AMD_F14_KR_A1 0x0000000000000200ull
#define AMD_F14_KR_B0 0x0000000000000400ull
// Family 14h Unknown stepping
#define AMD_F14_UNKNOWN 0x8000000000000000
#define AMD_F14_UNKNOWN 0x8000000000000000ull
#define AMD_F14_ON_Ax (AMD_F14_ON_A0 | AMD_F14_ON_A1)
#define AMD_F14_ON_Bx (AMD_F14_ON_B0)
#define AMD_F14_ON_Cx (AMD_F14_ON_C0)
#define AMD_F14_ON_ALL (AMD_F14_ON_Ax | AMD_F14_ON_Bx | AMD_F14_ON_Cx)
#define AMD_F14_ALL (AMD_F14_ON_Ax | AMD_F14_ON_Bx | AMD_F14_UNKNOWN)
#define AMD_F14_ALL (AMD_F14_ON_ALL | AMD_F14_UNKNOWN)
// Family 15h CPU_LOGICAL_ID.Revision equates
// -------------------------------------
// Family 15h OROCHI steppings
#define AMD_F15_OR_A0 0x0000000000000001
#define AMD_F15_OR_A0 0x0000000000000001ull
#define AMD_F15_OR_A1 0x0000000000000002ull
#define AMD_F15_OR_B0 0x0000000000000004ull
// Family 15h TN steppings
#define AMD_F15_TN_A0 0x0000000000000100ull
// Family 15h Unknown stepping
#define AMD_F15_UNKNOWN 0x8000000000000000
#define AMD_F15_UNKNOWN 0x8000000000000000ull
#define AMD_F15_OR_Ax (AMD_F15_OR_A0)
#define AMD_F15_OR_Ax (AMD_F15_OR_A0 | AMD_F15_OR_A1)
#define AMD_F15_OR_Bx AMD_F15_OR_B0
#define AMD_F15_OR_GT_Ax (AMD_F15_OR_Bx)
#define AMD_F15_OR_LT_B1 (AMD_F15_OR_Ax | AMD_F15_OR_B0)
#define AMD_F15_OR_ALL (AMD_F15_OR_Ax | AMD_F15_OR_Bx)
#define AMD_F15_ALL (AMD_F15_OR_Ax | AMD_F15_UNKNOWN)
#define AMD_F15_ALL (AMD_F15_OR_ALL | AMD_F15_UNKNOWN)
// Family 16h CPU_LOGICAL_ID.Revision equates
// TBD

4
src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/PreserveMailbox.c
View File

@ -157,7 +157,7 @@ PreserveMailboxes (
for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) {
for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) {
if (GetPciAddress (StdHeader, Socket, Module, &BaseAddress, &IgnoredStatus)) {
GetFeatureServicesOfSocket (&PreserveMailboxFamilyServiceTable, Socket, &FamilySpecificServices, StdHeader);
GetFeatureServicesOfSocket (&PreserveMailboxFamilyServiceTable, Socket, (const VOID **)&FamilySpecificServices, StdHeader);
ASSERT (FamilySpecificServices != NULL);
NextRegister = FamilySpecificServices->RegisterList;
while (NextRegister->AddressValue != ILLEGAL_SBDFO) {
@ -187,7 +187,7 @@ PreserveMailboxes (
for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) {
for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) {
if (GetPciAddress (StdHeader, Socket, Module, &BaseAddress, &IgnoredStatus)) {
GetFeatureServicesOfSocket (&PreserveMailboxFamilyServiceTable, Socket, &FamilySpecificServices, StdHeader);
GetFeatureServicesOfSocket (&PreserveMailboxFamilyServiceTable, Socket, (const VOID **)&FamilySpecificServices, StdHeader);
NextRegister = FamilySpecificServices->RegisterList;
while (NextRegister->AddressValue != ILLEGAL_SBDFO) {
ASSERT (RegisterEntryIndex <

14
src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuC6State.c
View File

@ -122,7 +122,7 @@ IsC6FeatureEnabled (
IsEnabled = TRUE;
for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) {
if (IsProcessorPresent (Socket, StdHeader)) {
GetFeatureServicesOfSocket (&C6FamilyServiceTable, Socket, &FamilyServices, StdHeader);
GetFeatureServicesOfSocket (&C6FamilyServiceTable, Socket, (const VOID **)&FamilyServices, StdHeader);
if ((FamilyServices == NULL) || !FamilyServices->IsC6Supported (FamilyServices, Socket, StdHeader)) {
IsEnabled = FALSE;
break;
@ -154,7 +154,7 @@ InitializeC6Feature (
{
UINT32 BscSocket;
UINT32 Ignored;
UINT32 BscCore;
UINT32 BscCoreNum;
UINT32 Core;
UINT32 Socket;
UINT32 NumberOfSockets;
@ -175,8 +175,8 @@ InitializeC6Feature (
if ((EntryPoint & (CPU_FEAT_AFTER_POST_MTRR_SYNC | CPU_FEAT_AFTER_RESUME_MTRR_SYNC)) != 0) {
// Load any required microcode patches on both normal boot and resume from S3.
IdentifyCore (StdHeader, &BscSocket, &Ignored, &BscCore, &IgnoredSts);
GetFeatureServicesOfSocket (&C6FamilyServiceTable, BscSocket, &C6FamilyServices, StdHeader);
IdentifyCore (StdHeader, &BscSocket, &Ignored, &BscCoreNum, &IgnoredSts);
GetFeatureServicesOfSocket (&C6FamilyServiceTable, BscSocket, (const VOID **)&C6FamilyServices, StdHeader);
if (C6FamilyServices != NULL) {
C6FamilyServices->ReloadMicrocodePatchAfterMemInit (StdHeader);
}
@ -189,13 +189,13 @@ InitializeC6Feature (
for (Socket = 0; Socket < NumberOfSockets; Socket++) {
if (IsProcessorPresent (Socket, StdHeader)) {
GetFeatureServicesOfSocket (&C6FamilyServiceTable, Socket, &C6FamilyServices, StdHeader);
GetFeatureServicesOfSocket (&C6FamilyServiceTable, Socket, (const VOID **)&C6FamilyServices, StdHeader);
if (C6FamilyServices != NULL) {
// run code on all APs
TaskPtr.FuncAddress.PfApTask = C6FamilyServices->ReloadMicrocodePatchAfterMemInit;
if (GetActiveCoresInGivenSocket (Socket, &NumberOfCores, StdHeader)) {
for (Core = 0; Core < NumberOfCores; Core++) {
if ((Socket != BscSocket) || (Core != BscCore)) {
if ((Socket != BscSocket) || (Core != BscCoreNum)) {
ApUtilRunCodeOnSocketCore ((UINT8) Socket, (UINT8) Core, &TaskPtr, StdHeader);
}
}
@ -230,7 +230,7 @@ EnableC6OnSocket (
IDS_HDT_CONSOLE (CPU_TRACE, " C6 is enabled\n");
GetFeatureServicesOfCurrentCore (&C6FamilyServiceTable, &FamilyServices, StdHeader);
GetFeatureServicesOfCurrentCore (&C6FamilyServiceTable, (const VOID **)&FamilyServices, StdHeader);
FamilyServices->InitializeC6 (FamilyServices,
*((UINT64 *) EntryPoint),
&CpuEarlyParams->PlatformConfig,

10
src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuCacheFlushOnHalt.c
View File

@ -97,6 +97,14 @@ EnableCacheFlushOnHaltOnSocket (
IN AMD_CONFIG_PARAMS *StdHeader,
IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams
);
AGESA_STATUS
InitializeCacheFlushOnHaltFeature (
IN UINT64 EntryPoint,
IN PLATFORM_CONFIGURATION *PlatformConfig,
IN OUT AMD_CONFIG_PARAMS *StdHeader
);
/*----------------------------------------------------------------------------------------
* P U B L I C F U N C T I O N S
*----------------------------------------------------------------------------------------
@ -178,7 +186,7 @@ EnableCacheFlushOnHaltOnSocket (
{
CPU_CFOH_FAMILY_SERVICES *FamilyServices;
GetFeatureServicesOfCurrentCore (&CacheFlushOnHaltFamilyServiceTable, &FamilyServices, StdHeader);
GetFeatureServicesOfCurrentCore (&CacheFlushOnHaltFamilyServiceTable, (const VOID **)&FamilyServices, StdHeader);
if (FamilyServices != NULL) {
FamilyServices->SetCacheFlushOnHaltRegister (FamilyServices, *((UINT64 *) EntryPoint), &CpuEarlyParams->PlatformConfig, StdHeader);
}

8
src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuCacheInit.c
View File

@ -220,8 +220,8 @@ AllocateExecutionCache (
IDS_HDT_CONSOLE (CPU_TRACE, " Cache size available for execution cache: 0x%x\n", AmdGetExeSize.AvailableExeCacheSize);
RemainingExecutionCacheSize = AmdGetExeSize.AvailableExeCacheSize - CurrentAllocatedExeCacheSize;
GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader);
FamilySpecificServices->GetCacheInfo (FamilySpecificServices, &CacheInfoPtr, &Ignored, StdHeader);
GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
FamilySpecificServices->GetCacheInfo (FamilySpecificServices, (const VOID **)&CacheInfoPtr, &Ignored, StdHeader);
// Process each request entry 0 to 2
for (i = 0; i < 3; i++) {
@ -451,8 +451,8 @@ AmdGetAvailableExeCacheSize (
AGESA_STATUS IgnoredStatus;
CPU_SPECIFIC_SERVICES *FamilySpecificServices;
GetCpuServicesOfCurrentCore (&FamilySpecificServices, &AmdGetExeSizeParams->StdHeader);
FamilySpecificServices->GetCacheInfo (FamilySpecificServices, &CacheInfoPtr, &Ignored, &AmdGetExeSizeParams->StdHeader);
GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, &AmdGetExeSizeParams->StdHeader);
FamilySpecificServices->GetCacheInfo (FamilySpecificServices, (const VOID **)&CacheInfoPtr, &Ignored, &AmdGetExeSizeParams->StdHeader);
// CAR_EXE mode is either "Limited by L2 size" or "Infinite Execution space"
ASSERT (CacheInfoPtr->CarExeType < MaxCarExeMode);
if (CacheInfoPtr->CarExeType == InfiniteExe) {

2
src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuCoreLeveling.c
View File

@ -318,7 +318,7 @@ CoreLevelingAtEarly (
// Set down core register
for (Socket = 0; Socket < NumberOfSockets; Socket++) {
if (IsProcessorPresent (Socket, StdHeader)) {
GetFeatureServicesOfSocket (&CoreLevelingFamilyServiceTable, Socket, &FamilySpecificServices, StdHeader);
GetFeatureServicesOfSocket (&CoreLevelingFamilyServiceTable, Socket, (const VOID **)&FamilySpecificServices, StdHeader);
if (FamilySpecificServices != NULL) {
for (Module = 0; Module < NumberOfModules; Module++) {
RegUpdated = FamilySpecificServices->SetDownCoreRegister (FamilySpecificServices, &Socket, &Module, &LeveledCores, CoreLevelMode, StdHeader);

4
src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuCpb.c
View File

@ -108,7 +108,7 @@ IsCpbFeatureEnabled (
if (PlatformConfig->CpbMode == CpbModeAuto) {
for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) {
if (IsProcessorPresent (Socket, StdHeader)) {
GetFeatureServicesOfSocket (&CpbFamilyServiceTable, Socket, &FamilyServices, StdHeader);
GetFeatureServicesOfSocket (&CpbFamilyServiceTable, Socket, (const VOID **)&FamilyServices, StdHeader);
if (FamilyServices != NULL) {
if (FamilyServices->IsCpbSupported (FamilyServices, PlatformConfig, Socket, StdHeader)) {
IsEnabled = TRUE;
@ -152,7 +152,7 @@ InitializeCpbFeature (
for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) {
if (IsProcessorPresent (Socket, StdHeader)) {
GetFeatureServicesOfSocket (&CpbFamilyServiceTable, Socket, &FamilyServices, StdHeader);
GetFeatureServicesOfSocket (&CpbFamilyServiceTable, Socket, (const VOID **)&FamilyServices, StdHeader);
if (FamilyServices != NULL) {
if (FamilyServices->IsCpbSupported (FamilyServices, PlatformConfig, Socket, StdHeader)) {
CalledStatus = FamilyServices->EnableCpbOnSocket (FamilyServices, PlatformConfig, EntryPoint, Socket, StdHeader);

36
src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuDmi.c
View File

@ -92,6 +92,28 @@ IntToString (
IN UINT8 SizeInByte
);
AGESA_STATUS
GetDmiInfoStub (
IN OUT AMD_CONFIG_PARAMS *StdHeader,
IN OUT DMI_INFO **DmiTable
);
AGESA_STATUS
GetDmiInfoMain (
IN OUT AMD_CONFIG_PARAMS *StdHeader,
IN OUT DMI_INFO **DmiTable
);
AGESA_STATUS
ReleaseDmiBufferStub (
IN OUT AMD_CONFIG_PARAMS *StdHeader
);
AGESA_STATUS
ReleaseDmiBuffer (
IN OUT AMD_CONFIG_PARAMS *StdHeader
);
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
@ -183,7 +205,7 @@ GetDmiInfoMain (
UINT16 NumberOfDimm;
UINT32 SocketNum;
UINT64 MsrData;
UINT64 MsrRegister;
UINT64 MsrReg;
BOOLEAN FamilyNotFound;
AGESA_STATUS Flag;
AGESA_STATUS CalledStatus;
@ -357,12 +379,12 @@ GetDmiInfoMain (
// TYPE 19
DmiBufferPtr->T19.StartingAddr = 0;
LibAmdMsrRead (TOP_MEM2, &MsrRegister, StdHeader);
if (MsrRegister == 0) {
LibAmdMsrRead (TOP_MEM, &MsrRegister, StdHeader);
DmiBufferPtr->T19.EndingAddr = (UINT32) (MsrRegister >> 10);
} else if (MsrRegister != 0) {
DmiBufferPtr->T19.EndingAddr = (UINT32) (MsrRegister >> 10);
LibAmdMsrRead (TOP_MEM2, &MsrReg, StdHeader);
if (MsrReg == 0) {
LibAmdMsrRead (TOP_MEM, &MsrReg, StdHeader);
DmiBufferPtr->T19.EndingAddr = (UINT32) (MsrReg >> 10);
} else if (MsrReg != 0) {
DmiBufferPtr->T19.EndingAddr = (UINT32) (MsrReg >> 10);
}
DmiBufferPtr->T19.PartitionWidth = 0xFF;

14
src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuFeatureLeveling.c
View File

@ -130,7 +130,7 @@ FeatureLeveling (
{
UINT32 BscSocket;
UINT32 Ignored;
UINT32 BscCore;
UINT32 BscCoreNum;
UINT32 Socket;
UINT32 Core;
UINT32 NumberOfSockets;
@ -151,7 +151,7 @@ FeatureLeveling (
*NeedLeveling = FALSE;
LibAmdMemFill (globalCpuFeatureList, 0xFF, sizeof (CPU_FEATURES_LIST), StdHeader);
IdentifyCore (StdHeader, &BscSocket, &Ignored, &BscCore, &IgnoredSts);
IdentifyCore (StdHeader, &BscSocket, &Ignored, &BscCoreNum, &IgnoredSts);
NumberOfSockets = GetPlatformNumberOfSockets ();
TaskPtr.FuncAddress.PfApTaskI = SaveFeatures;
@ -174,7 +174,7 @@ FeatureLeveling (
for (Socket = 0; Socket < NumberOfSockets; Socket++) {
if (GetActiveCoresInGivenSocket (Socket, &NumberOfCores, StdHeader)) {
for (Core = 0; Core < NumberOfCores; Core++) {
if ((Socket != BscSocket) || (Core != BscCore)) {
if ((Socket != BscSocket) || (Core != BscCoreNum)) {
ApUtilRunCodeOnSocketCore ((UINT8)Socket, (UINT8)Core, &TaskPtr, StdHeader);
}
}
@ -210,7 +210,7 @@ SaveFeatures (
CPU_SPECIFIC_SERVICES *FamilySpecificServices;
FamilySpecificServices = NULL;
GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader);
GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
FamilySpecificServices->SaveFeatures (FamilySpecificServices, cpuFeatureListPtr, StdHeader);
}
@ -235,7 +235,7 @@ WriteFeatures (
CPU_SPECIFIC_SERVICES *FamilySpecificServices;
FamilySpecificServices = NULL;
GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader);
GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
FamilySpecificServices->WriteFeatures (FamilySpecificServices, cpuFeatureListPtr, StdHeader);
}
@ -258,9 +258,9 @@ GetGlobalCpuFeatureListAddress (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT64 AddressValue;
VOID *AddressValue;
AddressValue = GLOBAL_CPU_FEATURE_LIST_TEMP_ADDR;
AddressValue = (VOID *)GLOBAL_CPU_FEATURE_LIST_TEMP_ADDR;
*Address = (UINT64 *)(AddressValue);
}

2
src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuFeatures.c
View File

@ -178,7 +178,7 @@ IsNonCoherentHt1 (
for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) {
if (IsProcessorPresent (Socket, StdHeader)) {
GetCpuServicesOfSocket (Socket, &CpuServices, StdHeader);
GetCpuServicesOfSocket (Socket, (const CPU_SPECIFIC_SERVICES **)&CpuServices, StdHeader);
for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) {
if (GetPciAddress (StdHeader, Socket, Module, &PciAddress, &AgesaStatus)) {
HtHostFeats.HtHostValue = 0;

8
src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuHtAssist.c
View File

@ -135,7 +135,7 @@ IsHtAssistEnabled (
if (IsEnabled) {
for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) {
if (IsProcessorPresent (Socket, StdHeader)) {
GetFeatureServicesOfSocket (&HtAssistFamilyServiceTable, Socket, &FamilyServices, StdHeader);
GetFeatureServicesOfSocket (&HtAssistFamilyServiceTable, Socket, (const VOID **)&FamilyServices, StdHeader);
if ((FamilyServices == NULL) || !FamilyServices->IsHtAssistSupported (FamilyServices, Socket, StdHeader)) {
IsEnabled = FALSE;
break;
@ -197,7 +197,7 @@ InitializeHtAssistFeature (
// cache is still enabled.
for (Socket = 0; Socket < MAX_SOCKETS_SUPPORTED; Socket++) {
if (IsProcessorPresent (Socket, StdHeader)) {
GetFeatureServicesOfSocket (&HtAssistFamilyServiceTable, Socket, &FamilyServices[Socket], StdHeader);
GetFeatureServicesOfSocket (&HtAssistFamilyServiceTable, Socket, (const VOID **)&FamilyServices[Socket], StdHeader);
} else {
FamilyServices[Socket] = NULL;
}
@ -303,7 +303,7 @@ DisableAllCaches (
UINT32 CR0Data;
HT_ASSIST_FAMILY_SERVICES *FamilyServices;
GetFeatureServicesOfCurrentCore (&HtAssistFamilyServiceTable, &FamilyServices, &ApExeParams->StdHeader);
GetFeatureServicesOfCurrentCore (&HtAssistFamilyServiceTable, (const VOID **)&FamilyServices, &ApExeParams->StdHeader);
FamilyServices->HookDisableCache (FamilyServices, &ApExeParams->StdHeader);
@ -341,7 +341,7 @@ EnableAllCaches (
CR0Data &= ~(0x60000000);
LibAmdWriteCpuReg (0, CR0Data);
GetFeatureServicesOfCurrentCore (&HtAssistFamilyServiceTable, &FamilyServices, &ApExeParams->StdHeader);
GetFeatureServicesOfCurrentCore (&HtAssistFamilyServiceTable, (const VOID **)&FamilyServices, &ApExeParams->StdHeader);
FamilyServices->HookEnableCache (FamilyServices, &ApExeParams->StdHeader);

4
src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuHwC1e.c
View File

@ -117,7 +117,7 @@ IsHwC1eFeatureEnabled (
if (GetNumberOfProcessors (StdHeader) == 1) {
GetApMailbox (&ApMailboxes.ApMailInfo.Info, StdHeader);
if (ApMailboxes.ApMailInfo.Fields.ModuleType == 0) {
GetFeatureServicesOfCurrentCore (&HwC1eFamilyServiceTable, &FamilyServices, StdHeader);
GetFeatureServicesOfCurrentCore (&HwC1eFamilyServiceTable, (const VOID **)&FamilyServices, StdHeader);
if (FamilyServices != NULL) {
IsEnabled = FamilyServices->IsHwC1eSupported (FamilyServices, StdHeader);
}
@ -157,7 +157,7 @@ InitializeHwC1eFeature (
IDS_HDT_CONSOLE (CPU_TRACE, " HW C1e is enabled\n");
if (IsWarmReset (StdHeader)) {
GetFeatureServicesOfCurrentCore (&HwC1eFamilyServiceTable, &FamilyServices, StdHeader);
GetFeatureServicesOfCurrentCore (&HwC1eFamilyServiceTable, (const VOID **)&FamilyServices, StdHeader);
CalledStatus = FamilyServices->InitializeHwC1e (FamilyServices, EntryPoint, PlatformConfig, StdHeader);
if (CalledStatus > AgesaStatus) {
AgesaStatus = CalledStatus;

4
src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuIoCstate.c
View File

@ -118,7 +118,7 @@ IsIoCstateFeatureSupported (
if ((PlatformConfig->CStateIoBaseAddress != 0) && (PlatformConfig->CStateIoBaseAddress <= 0xFFF8)) {
for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) {
if (IsProcessorPresent (Socket, StdHeader)) {
GetFeatureServicesOfSocket (&IoCstateFamilyServiceTable, Socket, &IoCstateServices, StdHeader);
GetFeatureServicesOfSocket (&IoCstateFamilyServiceTable, Socket, (const VOID **)&IoCstateServices, StdHeader);
if (IoCstateServices != NULL) {
if (IoCstateServices->IsIoCstateSupported (IoCstateServices, Socket, StdHeader)) {
IsSupported = TRUE;
@ -193,7 +193,7 @@ EnableIoCstateOnSocket (
{
IO_CSTATE_FAMILY_SERVICES *FamilyServices;
GetFeatureServicesOfCurrentCore (&IoCstateFamilyServiceTable, &FamilyServices, StdHeader);
GetFeatureServicesOfCurrentCore (&IoCstateFamilyServiceTable, (const VOID **)&FamilyServices, StdHeader);
FamilyServices->InitializeIoCstate (FamilyServices,
*((UINT64 *) EntryPoint),
&CpuEarlyParams->PlatformConfig,

4
src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuLowPwrPstate.c
View File

@ -116,7 +116,7 @@ IsLowPwrPstateFeatureSupported (
IsSupported = FALSE;
for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) {
if (IsProcessorPresent (Socket, StdHeader)) {
GetFeatureServicesOfSocket (&LowPwrPstateFamilyServiceTable, Socket, &FamilyServices, StdHeader);
GetFeatureServicesOfSocket (&LowPwrPstateFamilyServiceTable, Socket, (const VOID **)&FamilyServices, StdHeader);
if (FamilyServices != NULL) {
if (FamilyServices->IsLowPwrPstateSupported (FamilyServices, PlatformConfig, Socket, StdHeader)) {
IsSupported = TRUE;
@ -189,7 +189,7 @@ EnableLowPwrPstateOnSocket (
{
LOW_PWR_PSTATE_FAMILY_SERVICES *FamilyServices;
GetFeatureServicesOfCurrentCore (&LowPwrPstateFamilyServiceTable, &FamilyServices, StdHeader);
GetFeatureServicesOfCurrentCore (&LowPwrPstateFamilyServiceTable, (const VOID **)&FamilyServices, StdHeader);
FamilyServices->EnableLowPwrPstate (FamilyServices,
&CpuEarlyParams->PlatformConfig,
*((UINT64 *) EntryPoint),

4
src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuMsgBasedC1e.c
View File

@ -127,7 +127,7 @@ IsMsgBasedC1eFeatureEnabled (
} else {
for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) {
if (IsProcessorPresent (Socket, StdHeader)) {
GetFeatureServicesOfSocket (&MsgBasedC1eFamilyServiceTable, Socket, &FamilyServices, StdHeader);
GetFeatureServicesOfSocket (&MsgBasedC1eFamilyServiceTable, Socket, (const VOID **)&FamilyServices, StdHeader);
if ((FamilyServices == NULL) || !FamilyServices->IsMsgBasedC1eSupported (FamilyServices, Socket, StdHeader)) {
IsEnabled = FALSE;
break;
@ -197,7 +197,7 @@ EnableMsgC1eOnSocket (
{
MSG_BASED_C1E_FAMILY_SERVICES *FamilyServices;
GetFeatureServicesOfCurrentCore (&MsgBasedC1eFamilyServiceTable, &FamilyServices, StdHeader);
GetFeatureServicesOfCurrentCore (&MsgBasedC1eFamilyServiceTable, (const VOID **)&FamilyServices, StdHeader);
FamilyServices->InitializeMsgBasedC1e (FamilyServices,
*((UINT64 *) EntryPoint),
&CpuEarlyParams->PlatformConfig,

16
src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuPstateGather.c
View File

@ -89,6 +89,18 @@ extern CPU_FAMILY_SUPPORT_TABLE PstateFamilyServiceTable;
*----------------------------------------------------------------------------
*/
AGESA_STATUS
PStateGatherStub (
IN AMD_CONFIG_PARAMS *StdHeader,
IN OUT S_CPU_AMD_PSTATE *PStateStrucPtr
);
AGESA_STATUS
PStateGatherMain (
IN AMD_CONFIG_PARAMS *StdHeader,
IN OUT S_CPU_AMD_PSTATE *PStateStrucPtr
);
/*----------------------------------------------------------------------------
* EXPORTED FUNCTIONS
*
@ -204,7 +216,7 @@ PStateGatherMain (
ASSERT (IsBsp (StdHeader, &IgnoredSts));
FamilyServices = NULL;
GetFeatureServicesOfCurrentCore (&PstateFamilyServiceTable, &FamilyServices, StdHeader);
GetFeatureServicesOfCurrentCore (&PstateFamilyServiceTable, (const VOID **)&FamilyServices, StdHeader);
ASSERT (FamilyServices != NULL);
PopulatedSockets = 1;
@ -306,7 +318,7 @@ PStateGather (
FamilyServices = NULL;
PStateEnabled = FALSE;
GetFeatureServicesOfCurrentCore (&PstateFamilyServiceTable, &FamilyServices, StdHeader);
GetFeatureServicesOfCurrentCore (&PstateFamilyServiceTable, (const VOID **)&FamilyServices, StdHeader);
ASSERT (FamilyServices != NULL);
//

34
src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuPstateLeveling.c
View File

@ -107,6 +107,24 @@ PutCoreInPState0 (
IN AMD_CONFIG_PARAMS *StdHeader
);
AGESA_STATUS
PStateLevelingStub (
IN OUT S_CPU_AMD_PSTATE *PStateStrucPtr,
IN AMD_CONFIG_PARAMS *StdHeader
);
AGESA_STATUS
PStateLevelingMain (
IN OUT S_CPU_AMD_PSTATE *PStateStrucPtr,
IN AMD_CONFIG_PARAMS *StdHeader
);
VOID
CorePstateRegModify (
IN VOID *CpuAmdPState,
IN AMD_CONFIG_PARAMS *StdHeader
);
/**
*---------------------------------------------------------------------------------------
@ -874,7 +892,7 @@ PutAllCoreInPState0 (
AP_TASK TaskPtr;
UINT32 BscSocket;
UINT32 Ignored;
UINT32 BscCore;
UINT32 BscCoreNum;
UINT32 Core;
UINT32 Socket;
UINT32 NumberOfSockets;
@ -887,7 +905,7 @@ PutAllCoreInPState0 (
TaskPtr.DataTransfer.DataPtr = PStateBufferPtr;
TaskPtr.DataTransfer.DataTransferFlags = DATA_IN_MEMORY;
IdentifyCore (StdHeader, &BscSocket, &Ignored, &BscCore, &IgnoredSts);
IdentifyCore (StdHeader, &BscSocket, &Ignored, &BscCoreNum, &IgnoredSts);
NumberOfSockets = GetPlatformNumberOfSockets ();
PutCoreInPState0 (PStateBufferPtr, StdHeader);
@ -895,7 +913,7 @@ PutAllCoreInPState0 (
for (Socket = 0; Socket < NumberOfSockets; Socket++) {
if (GetActiveCoresInGivenSocket (Socket, &NumberOfCores, StdHeader)) {
for (Core = 0; Core < NumberOfCores; Core++) {
if ((Socket != (UINT32) BscSocket) || (Core != (UINT32) BscCore)) {
if ((Socket != (UINT32) BscSocket) || (Core != (UINT32) BscCoreNum)) {
ApUtilRunCodeOnSocketCore ((UINT8) Socket, (UINT8) Core, &TaskPtr, StdHeader);
}
}
@ -931,7 +949,7 @@ CorePstateRegModify (
PSTATE_CPU_FAMILY_SERVICES *FamilySpecificServices;
FamilySpecificServices = NULL;
GetFeatureServicesOfCurrentCore (&PstateFamilyServiceTable, &FamilySpecificServices, StdHeader);
GetFeatureServicesOfCurrentCore (&PstateFamilyServiceTable, (const VOID **)&FamilySpecificServices, StdHeader);
ASSERT (FamilySpecificServices != NULL)
FamilySpecificServices->SetPStateLevelReg (FamilySpecificServices, (S_CPU_AMD_PSTATE *) CpuAmdPState, StdHeader);
}
@ -956,7 +974,7 @@ StartPstateMsrModify (
AP_TASK TaskPtr;
UINT32 BscSocket;
UINT32 Ignored;
UINT32 BscCore;
UINT32 BscCoreNum;
UINT32 Core;
UINT32 Socket;
UINT32 NumberOfSockets;
@ -969,7 +987,7 @@ StartPstateMsrModify (
TaskPtr.DataTransfer.DataPtr = CpuAmdPState;
TaskPtr.DataTransfer.DataTransferFlags = DATA_IN_MEMORY;
IdentifyCore (StdHeader, &BscSocket, &Ignored, &BscCore, &IgnoredSts);
IdentifyCore (StdHeader, &BscSocket, &Ignored, &BscCoreNum, &IgnoredSts);
NumberOfSockets = GetPlatformNumberOfSockets ();
CorePstateRegModify (CpuAmdPState, StdHeader);
@ -977,7 +995,7 @@ StartPstateMsrModify (
for (Socket = 0; Socket < NumberOfSockets; Socket++) {
if (GetActiveCoresInGivenSocket (Socket, &NumberOfCores, StdHeader)) {
for (Core = 0; Core < NumberOfCores; Core++) {
if ((Socket != (UINT32) BscSocket) || (Core != (UINT32) BscCore)) {
if ((Socket != (UINT32) BscSocket) || (Core != (UINT32) BscCoreNum)) {
ApUtilRunCodeOnSocketCore ((UINT8) Socket, (UINT8) Core, &TaskPtr, StdHeader);
}
}
@ -1067,7 +1085,7 @@ PutCoreInPState0 (
return;
}
GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader);
GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
FamilySpecificServices->TransitionPstate (FamilySpecificServices, (UINT8) 0, (BOOLEAN) FALSE, StdHeader);
}

61
src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuPstateTables.c
View File

@ -81,14 +81,14 @@ extern CPU_FAMILY_SUPPORT_TABLE IoCstateFamilyServiceTable;
STATIC ACPI_TABLE_HEADER ROMDATA CpuSsdtHdrStruct =
{
'S','S','D','T',
{'S','S','D','T'},
0,
1,
0,
'A','M','D',' ',' ',' ',
'P','O','W','E','R','N','O','W',
{'A','M','D',' ',' ',' '},
{'P','O','W','E','R','N','O','W'},
1,
'A','M','D',' ',
{'A','M','D',' '},
1
};
@ -105,6 +105,47 @@ STATIC ACPI_TABLE_HEADER ROMDATA CpuSsdtHdrStruct =
*----------------------------------------------------------------------------
*/
UINT32
CalAcpiTablesSize (
IN S_CPU_AMD_PSTATE *AmdPstatePtr,
IN PLATFORM_CONFIGURATION *PlatformConfig,
IN AMD_CONFIG_PARAMS *StdHeader
);
AGESA_STATUS
GenerateSsdtStub (
IN AMD_CONFIG_PARAMS *StdHeader,
IN PLATFORM_CONFIGURATION *PlatformConfig,
IN OUT VOID **SsdtPtr
);
UINT32
CreateAcpiTablesStub (
IN PLATFORM_CONFIGURATION *PlatformConfig,
IN PSTATE_LEVELING *PStateLevelingBuffer,
IN OUT VOID **SsdtPtr,
IN UINT8 LocalApicId,
IN AMD_CONFIG_PARAMS *StdHeader
);
UINT32
CreatePStateAcpiTables (
IN PLATFORM_CONFIGURATION *PlatformConfig,
IN PSTATE_LEVELING *PStateLevelingBuffer,
IN OUT VOID **SsdtPtr,
IN UINT8 LocalApicId,
IN AMD_CONFIG_PARAMS *StdHeader
);
UINT32
CreateCStateAcpiTables (
IN PLATFORM_CONFIGURATION *PlatformConfig,
IN PSTATE_LEVELING *PStateLevelingBuffer,
IN OUT VOID **SsdtPtr,
IN UINT8 LocalApicId,
IN AMD_CONFIG_PARAMS *StdHeader
);
/**
*---------------------------------------------------------------------------------------
*
@ -147,7 +188,7 @@ CalAcpiTablesSize (
MaxSocketNumberInSystem = AmdPstatePtr->TotalSocketInSystem;
if (IsFeatureEnabled (IoCstate, PlatformConfig, StdHeader)) {
GetFeatureServicesOfCurrentCore (&IoCstateFamilyServiceTable, &IoCstateFamilyServices, StdHeader);
GetFeatureServicesOfCurrentCore (&IoCstateFamilyServiceTable, (const VOID **)&IoCstateFamilyServices, StdHeader);
// If we're supporting multiple families, only proceed when IO Cstate family services are available
if (IoCstateFamilyServices != NULL) {
CstateAcpiObjSize = IoCstateFamilyServices->GetAcpiCstObj (IoCstateFamilyServices, PlatformConfig, StdHeader);
@ -333,8 +374,8 @@ GenerateSsdt (
}
ScopeAcpiTablesStructPtr->ScopeNamePt1b__ = SCOPE_NAME__;
ASSERT ((PlatformConfig->ProcessorScopeName0 >= 'A') && (PlatformConfig->ProcessorScopeName0 <= 'Z'))
ASSERT ((PlatformConfig->ProcessorScopeName1 >= 'A') && (PlatformConfig->ProcessorScopeName1 <= 'Z') || \
(PlatformConfig->ProcessorScopeName1 >= '0') && (PlatformConfig->ProcessorScopeName1 <= '9') || \
ASSERT (((PlatformConfig->ProcessorScopeName1 >= 'A') && (PlatformConfig->ProcessorScopeName1 <= 'Z')) || \
((PlatformConfig->ProcessorScopeName1 >= '0') && (PlatformConfig->ProcessorScopeName1 <= '9')) || \
(PlatformConfig->ProcessorScopeName1 == '_'))
ScopeAcpiTablesStructPtr->ScopeNamePt2a_C = PlatformConfig->ProcessorScopeName0;
@ -555,7 +596,7 @@ CreatePStateAcpiTables (
// Calculate PCI address for socket only
GetPciAddress (StdHeader, (UINT32) PStateLevelingBuffer->SocketNumber, 0, &PciAddress, &IgnoredStatus);
TransAndBusMastLatency = 0;
GetFeatureServicesOfSocket (&PstateFamilyServiceTable, (UINT32) PStateLevelingBuffer->SocketNumber, &FamilyServices, StdHeader);
GetFeatureServicesOfSocket (&PstateFamilyServiceTable, (UINT32) PStateLevelingBuffer->SocketNumber, (const VOID **)&FamilyServices, StdHeader);
ASSERT (FamilyServices != NULL)
FamilyServices->GetPstateLatency ( FamilyServices,
PStateLevelingBuffer,
@ -698,7 +739,7 @@ CreatePStateAcpiTables (
pPsdBodyAcpiTables = (PSD_BODY *) pXpssBodyAcpiTables;
// Get Total Cores Per Node
if (GetActiveCoresInGivenSocket ((UINT32) PStateLevelingBuffer->SocketNumber, &CoreCount1, StdHeader)) {
GetFeatureServicesOfSocket (&PstateFamilyServiceTable, (UINT32) PStateLevelingBuffer->SocketNumber, &FamilyServices, StdHeader);
GetFeatureServicesOfSocket (&PstateFamilyServiceTable, (UINT32) PStateLevelingBuffer->SocketNumber, (const VOID **)&FamilyServices, StdHeader);
ASSERT (FamilyServices != NULL)
if ((CoreCount1 != 1) && (OptionPstateLateConfiguration.CfgPstatePsd) &&
FamilyServices->IsPstatePsdNeeded (FamilyServices, PlatformConfig, StdHeader)) {
@ -819,7 +860,7 @@ CreateCStateAcpiTables (
ObjSize = 0;
if (IsFeatureEnabled (IoCstate, PlatformConfig, StdHeader)) {
GetFeatureServicesOfCurrentCore (&IoCstateFamilyServiceTable, &IoCstateFamilyServices, StdHeader);
GetFeatureServicesOfCurrentCore (&IoCstateFamilyServiceTable, (const VOID **)&IoCstateFamilyServices, StdHeader);
// If we're supporting multiple families, only proceed when IO Cstate family services are available
if (IoCstateFamilyServices != NULL) {
IoCstateFamilyServices->CreateAcpiCstObj (IoCstateFamilyServices, LocalApicId, SsdtPtr, StdHeader);

34
src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuSlit.c
View File

@ -77,14 +77,14 @@ extern OPTION_SLIT_CONFIGURATION OptionSlitConfiguration; // global user config
STATIC ACPI_TABLE_HEADER ROMDATA CpuSlitHdrStruct =
{
'S','L','I','T',
{'S','L','I','T'},
0,
1,
0,
'A','M','D',' ',' ',' ',
'A','G','E','S','A',' ',' ',' ',
{'A','M','D',' ',' ',' '},
{'A','G','E','S','A',' ',' ',' '},
1,
'A','M','D',' ',
{'A','M','D',' '},
1
};
@ -97,6 +97,21 @@ STATIC ACPI_TABLE_HEADER ROMDATA CpuSlitHdrStruct =
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
AGESA_STATUS
GetAcpiSlitStub (
IN OUT AMD_CONFIG_PARAMS *StdHeader,
IN PLATFORM_CONFIGURATION *PlatformConfig,
IN OUT VOID **SlitPtr
);
AGESA_STATUS
GetAcpiSlitMain (
IN OUT AMD_CONFIG_PARAMS *StdHeader,
IN PLATFORM_CONFIGURATION *PlatformConfig,
IN OUT VOID **SlitPtr
);
VOID
STATIC
AcpiSlitHBufferFind (
@ -104,12 +119,21 @@ AcpiSlitHBufferFind (
IN UINT8 **SocketTopologyPtr
);
AGESA_STATUS
ReleaseSlitBufferStub (
IN OUT AMD_CONFIG_PARAMS *StdHeader
);
AGESA_STATUS
ReleaseSlitBuffer (
IN OUT AMD_CONFIG_PARAMS *StdHeader
);
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------

20
src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuSrat.c
View File

@ -81,14 +81,14 @@ extern OPTION_SRAT_CONFIGURATION OptionSratConfiguration; // global user config
*/
STATIC CPU_SRAT_HEADER ROMDATA CpuSratHdrStruct =
{
'S','R','A','T',
{'S','R','A','T'},
0,
2,
0,
'A','M','D',' ',' ',' ',
'A','G','E','S','A',' ',' ',' ',
{'A','M','D',' ',' ',' '},
{'A','G','E','S','A',' ',' ',' '},
1,
'A','M','D',' ',
{'A','M','D',' '},
1,
1,
{0, 0, 0, 0, 0, 0, 0, 0}
@ -98,6 +98,18 @@ STATIC CPU_SRAT_HEADER ROMDATA CpuSratHdrStruct =
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
AGESA_STATUS
GetAcpiSratStub (
IN OUT AMD_CONFIG_PARAMS *StdHeader,
IN OUT VOID **SratPtr
);
AGESA_STATUS
GetAcpiSratMain (
IN OUT AMD_CONFIG_PARAMS *StdHeader,
IN OUT VOID **SratPtr
);
UINT8
STATIC
*MakeApicEntry (

4
src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuSwC1e.c
View File

@ -121,7 +121,7 @@ IsSwC1eFeatureEnabled (
if (GetNumberOfProcessors (StdHeader) == 1) {
GetApMailbox (&ApMailboxes.ApMailInfo.Info, StdHeader);
if (ApMailboxes.ApMailInfo.Fields.ModuleType == 0) {
GetFeatureServicesOfCurrentCore (&SwC1eFamilyServiceTable, &SwFamilyServices, StdHeader);
GetFeatureServicesOfCurrentCore (&SwC1eFamilyServiceTable, (const VOID **)&SwFamilyServices, StdHeader);
if (SwFamilyServices != NULL) {
IsEnabled = SwFamilyServices->IsSwC1eSupported (SwFamilyServices, StdHeader);
}
@ -160,7 +160,7 @@ InitializeSwC1eFeature (
IDS_HDT_CONSOLE (CPU_TRACE, " SW C1e is enabled\n");
if (IsWarmReset (StdHeader)) {
GetFeatureServicesOfCurrentCore (&SwC1eFamilyServiceTable, &FamilyServices, StdHeader);
GetFeatureServicesOfCurrentCore (&SwC1eFamilyServiceTable, (const VOID **)&FamilyServices, StdHeader);
AgesaStatus = FamilyServices->InitializeSwC1e (FamilyServices, EntryPoint, PlatformConfig, StdHeader);
}

18
src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuWhea.c
View File

@ -85,6 +85,20 @@ CreateHestBank (
IN AMD_WHEA_INIT_DATA *WheaInitDataPtr
);
AGESA_STATUS
GetAcpiWheaStub (
IN OUT AMD_CONFIG_PARAMS *StdHeader,
IN OUT VOID **WheaMcePtr,
IN OUT VOID **WheaCmcPtr
);
AGESA_STATUS
GetAcpiWheaMain (
IN OUT AMD_CONFIG_PARAMS *StdHeader,
IN OUT VOID **WheaMcePtr,
IN OUT VOID **WheaCmcPtr
);
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
@ -178,8 +192,8 @@ GetAcpiWheaMain (
return AGESA_ERROR;
}
GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader);
FamilySpecificServices->GetWheaInitData (FamilySpecificServices, &WheaInitDataPtr, &Entries, StdHeader);
GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
FamilySpecificServices->GetWheaInitData (FamilySpecificServices, (const VOID **)&WheaInitDataPtr, &Entries, StdHeader);
ASSERT (WheaInitDataPtr->HestBankNum <= BankNum);

8
src/vendorcode/amd/agesa/f14/Proc/CPU/S3.c
View File

@ -214,11 +214,11 @@ SaveDeviceContext (
{
DEVICE_DESCRIPTORS Device;
UINT16 i;
UINT64 StartAddress;
UINT64 EndAddress;
VOID *StartAddress;
VOID *EndAddress;
VOID *OrMask;
StartAddress = (UINT64) DeviceList;
StartAddress = DeviceList;
Device.CommonDeviceHeader = (DEVICE_DESCRIPTOR *) &DeviceList[1];
OrMask = (UINT8 *) DeviceList + DeviceList->RelativeOrMaskOffset;
@ -282,7 +282,7 @@ SaveDeviceContext (
break;
}
}
EndAddress = (UINT64) OrMask;
EndAddress = (VOID *) OrMask;
*ActualBufferSize = (UINT32) (EndAddress - StartAddress);
}

31
src/vendorcode/amd/agesa/f14/Proc/CPU/Table.c
View File

@ -83,6 +83,13 @@ extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration;
*----------------------------------------------------------------------------------------
*/
VOID
SetRegistersFromTablesAtEarly (
IN CPU_SPECIFIC_SERVICES *FamilyServices,
IN AMD_CPU_EARLY_PARAMS *EarlyParams,
IN AMD_CONFIG_PARAMS *StdHeader
);
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
@ -123,7 +130,7 @@ STATIC
TABLE_ENTRY_FIELDS *Entries;
ASSERT ((FamilySpecificServices != NULL) && (StdHeader != NULL));
ASSERT (Selector < TableEntryTypeMax);
ASSERT (Selector < TableCoreSelectorMax);
NextTable = *RegisterTableHandle;
if (NextTable == NULL) {
@ -239,7 +246,7 @@ GetPerformanceFeatures (
}
// Get some family, model specific performance type info.
GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader);
GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
ASSERT (FamilySpecificServices != NULL);
// Is the Northbridge P-State feature enabled
@ -400,7 +407,7 @@ SetRegisterForHtPhyEntry (
IdentifyCore (StdHeader, &MySocket, &MyModule, &Ignored, &IgnoredStatus);
GetPciAddress (StdHeader, MySocket, MyModule, &CapabilitySet, &IgnoredStatus);
GetLogicalIdOfCurrentCore (&CpuFamilyRevision, StdHeader);
GetCpuServicesFromLogicalId (&CpuFamilyRevision, &FamilySpecificServices, StdHeader);
GetCpuServicesFromLogicalId (&CpuFamilyRevision, (const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
Link = 0;
while (FamilySpecificServices->NextLinkHasHtPhyFeats (
FamilySpecificServices,
@ -461,7 +468,7 @@ SetRegisterForHtPhyRangeEntry (
IdentifyCore (StdHeader, &MySocket, &MyModule, &Ignored, &IgnoredStatus);
GetPciAddress (StdHeader, MySocket, MyModule, &CapabilitySet, &IgnoredStatus);
GetLogicalIdOfCurrentCore (&CpuFamilyRevision, StdHeader);
GetCpuServicesFromLogicalId (&CpuFamilyRevision, &FamilySpecificServices, StdHeader);
GetCpuServicesFromLogicalId (&CpuFamilyRevision, (const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
Link = 0;
while (FamilySpecificServices->NextLinkHasHtPhyFeats (
FamilySpecificServices,
@ -646,7 +653,7 @@ SetRegisterForDeemphasisEntry (
IdentifyCore (StdHeader, &MySocket, &MyModule, &Ignored, &IgnoredStatus);
GetPciAddress (StdHeader, MySocket, MyModule, &CapabilitySet, &IgnoredStatus);
GetLogicalIdOfCurrentCore (&CpuFamilyRevision, StdHeader);
GetCpuServicesFromLogicalId (&CpuFamilyRevision, &FamilySpecificServices, StdHeader);
GetCpuServicesFromLogicalId (&CpuFamilyRevision, (const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
Link = 0;
while (FamilySpecificServices->NextLinkHasHtPhyFeats (
FamilySpecificServices,
@ -726,7 +733,7 @@ SetRegisterForHtPhyFreqEntry (
IdentifyCore (StdHeader, &MySocket, &MyModule, &Ignored, &IgnoredStatus);
GetPciAddress (StdHeader, MySocket, MyModule, &CapabilitySet, &IgnoredStatus);
GetLogicalIdOfCurrentCore (&CpuFamilyRevision, StdHeader);
GetCpuServicesFromLogicalId (&CpuFamilyRevision, &FamilySpecificServices, StdHeader);
GetCpuServicesFromLogicalId (&CpuFamilyRevision, (const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
Link = 0;
while (FamilySpecificServices->NextLinkHasHtPhyFeats (
FamilySpecificServices,
@ -903,7 +910,7 @@ SetRegisterForHtHostEntry (
IdentifyCore (StdHeader, &MySocket, &MyModule, &Ignored, &IgnoredStatus);
GetPciAddress (StdHeader, MySocket, MyModule, &CapabilitySet, &IgnoredStatus);
GetLogicalIdOfCurrentCore (&CpuFamilyRevision, StdHeader);
GetCpuServicesFromLogicalId (&CpuFamilyRevision, &FamilySpecificServices, StdHeader);
GetCpuServicesFromLogicalId (&CpuFamilyRevision, (const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
Link = 0;
while (FamilySpecificServices->GetNextHtLinkFeatures (FamilySpecificServices, &Link, &CapabilitySet, &HtHostFeats, StdHeader)) {
if (DoesEntryTypeSpecificInfoMatch (HtHostFeats.HtHostValue, Entry->HtHostEntry.TypeFeats.HtHostValue)) {
@ -1008,7 +1015,7 @@ SetRegisterForHtLinkTokenEntry (
IdentifyCore (StdHeader, &MySocket, &MyModule, &Ignored, &IgnoredStatus);
GetPciAddress (StdHeader, MySocket, MyModule, &CapabilitySet, &IgnoredStatus);
GetLogicalIdOfCurrentCore (&CpuFamilyRevision, StdHeader);
GetCpuServicesFromLogicalId (&CpuFamilyRevision, &FamilySpecificServices, StdHeader);
GetCpuServicesFromLogicalId (&CpuFamilyRevision, (const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
// Check if the actual processor count and SystemDegree are in either range.
ProcessorCount = GetNumberOfProcessors (StdHeader);
@ -1259,7 +1266,7 @@ SetRegisterForHtFeaturePciEntry (
IdentifyCore (StdHeader, &MySocket, &MyModule, &Ignored, &IgnoredStatus);
GetPciAddress (StdHeader, MySocket, MyModule, &CapabilitySet, &IgnoredStatus);
GetLogicalIdOfCurrentCore (&CpuFamilyRevision, StdHeader);
GetCpuServicesFromLogicalId (&CpuFamilyRevision, &FamilySpecificServices, StdHeader);
GetCpuServicesFromLogicalId (&CpuFamilyRevision, (const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
ASSERT ((Entry->HtFeatPciEntry.PackageType.PackageTypeValue & ~(PACKAGE_TYPE_ALL)) == 0);
@ -1323,7 +1330,7 @@ SetRegisterForHtLinkPciEntry (
IdentifyCore (StdHeader, &MySocket, &MyModule, &Ignored, &IgnoredStatus);
GetPciAddress (StdHeader, MySocket, MyModule, &CapabilitySet, &IgnoredStatus);
GetLogicalIdOfCurrentCore (&CpuFamilyRevision, StdHeader);
GetCpuServicesFromLogicalId (&CpuFamilyRevision, &FamilySpecificServices, StdHeader);
GetCpuServicesFromLogicalId (&CpuFamilyRevision, (const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
Link = 0;
while (FamilySpecificServices->GetNextHtLinkFeatures (FamilySpecificServices, &Link, &CapabilitySet, &HtHostFeats, StdHeader)) {
@ -1424,7 +1431,7 @@ GetPlatformFeatures (
//
// Get some specific platform type info, VC...etc.
//
GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader);
GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
ASSERT (FamilySpecificServices != NULL);
FamilySpecificServices->GetPlatformTypeSpecificInfo (FamilySpecificServices, Features, StdHeader);
@ -1601,7 +1608,7 @@ SetRegistersFromTables (
PlatformFeatures.PlatformValue = 0;
GetLogicalIdOfCurrentCore (&CpuLogicalId, StdHeader);
GetPlatformFeatures (&PlatformFeatures, PlatformConfig, StdHeader);
GetCpuServicesFromLogicalId (&CpuLogicalId, &FamilySpecificServices, StdHeader);
GetCpuServicesFromLogicalId (&CpuLogicalId, (const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
// Build a non-sparse table of implementer methods, so we don't have to keep searching.
// It is a bug to not include a descriptor for a type that is in the table (but the

Some files were not shown because too many files have changed in this diff Show More