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soc/intel/alderlake: Refactor SoC code to maintain CPU and PCH PCIE RPs

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List of changes:
1. Create new Kconfig MAX_CPU_ROOT_PORTS and MAX_PCH_ROOT_PORTS as per
EDS.
2. Add new chip variable to enable/disable CPU PCIE RPs from mainboards.
3. Rename PcieRpEnable to PchPcieRpEnable.
4. Enable CPU RPs as below in mainboard devicetree.cb

RP1: PEG60 : 0:6:0 : CPU SSD1
RP2: PEG10 : 0:1:0 : x8 CPU Slot
RP3: PEG62 : 0:6:2 : CPU SSD2

Change-Id: I92123450bd7cfb2e70aae8de03053672a7772451
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49136
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Subrata Banik
2021-01-09 16:17:45 +05:30
parent 9a1b720b1f
commit 85144d9002
5 changed files with 42 additions and 21 deletions
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2
src/soc/intel/alderlake/fsp_params.c
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@@ -270,7 +270,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
/* Enable Hybrid storage auto detection */
params->HybridStorageMode = config->HybridStorageMode;
for (i = 0; i < CONFIG_MAX_ROOT_PORTS; i++) {
for (i = 0; i < CONFIG_MAX_PCH_ROOT_PORTS; i++) {
params->PcieRpL1Substates[i] =
get_l1_substate_control(config->PcieRpL1Substates[i]);
params->PcieRpLtrEnable[i] = config->PcieRpLtrEnable[i];