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soc/intel/apollolake: Provide interface to update TCC offset

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This change provides an interface for apollolake to set TCC before
BIOS reset complete happens in romstage.

With this change, we can add code to update Tcc in devicetree.

BUG=b:117789732
TEST=Match the result from TAT UI

Change-Id: I4419d3bbe2628fcb26ef81828d6325fc952dbabc
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/29351
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
This commit is contained in:
John Su
2018-11-06 10:51:43 +08:00
committed by Furquan Shaikh
parent 63952e1060
commit 85376bfd9b
3 changed files with 54 additions and 19 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
src/soc/intel/apollolake/chip.h
View File

@@ -112,6 +112,9 @@ struct soc_intel_apollolake_config {
/* Enable DPTF support */
int dptf_enable;
/* TCC activation offset value in degrees Celsius */
int tcc_offset;
/* PL1 override value in mW for APL */
uint16_t tdp_pl1_override_mw;
/* PL2 override value in mW for APL */

40
src/soc/intel/apollolake/romstage.c
View File

@@ -28,29 +28,30 @@
#include <console/console.h>
#include <cpu/x86/mtrr.h>
#include <cpu/x86/pae.h>
#include <delay.h>
#include <device/pci_def.h>
#include <device/resource.h>
#include <intelblocks/lpc_lib.h>
#include <fsp/api.h>
#include <fsp/memmap.h>
#include <fsp/util.h>
#include <intelblocks/cpulib.h>
#include <intelblocks/lpc_lib.h>
#include <intelblocks/msr.h>
#include <intelblocks/pmclib.h>
#include <intelblocks/smm.h>
#include <intelblocks/systemagent.h>
#include <intelblocks/pmclib.h>
#include <mrc_cache.h>
#include <soc/cpu.h>
#include <soc/iomap.h>
#include <soc/meminit.h>
#include <soc/systemagent.h>
#include <soc/pci_devs.h>
#include <soc/pm.h>
#include <soc/romstage.h>
#include <soc/systemagent.h>
#include <spi_flash.h>
#include <string.h>
#include <timestamp.h>
#include <timer.h>
#include <delay.h>
#include <timestamp.h>
#include "chip.h"
static const uint8_t hob_variable_guid[16] = {
@@ -99,6 +100,32 @@ static void soc_early_romstage_init(void)
lpc_io_setup_comm_a_b();
}
/* Thermal throttle activation offset */
static void configure_thermal_target(void)
{
const struct device *dev = dev_find_slot(0, SA_DEVFN_ROOT);
if (!dev) {
printk(BIOS_ERR, "Could not find SOC devicetree config\n");
return;
}
const config_t *conf = dev->chip_info;
if (!dev->chip_info) {
printk(BIOS_ERR, "Could not find chip info\n");
return;
}
msr_t msr;
if (!conf->tcc_offset)
return;
msr = rdmsr(MSR_TEMPERATURE_TARGET);
/* Bits 27:24 */
msr.lo &= ~(TEMPERATURE_TCC_MASK << TEMPERATURE_TCC_SHIFT);
msr.lo |= (conf->tcc_offset & TEMPERATURE_TCC_MASK)
<< TEMPERATURE_TCC_SHIFT;
wrmsr(MSR_TEMPERATURE_TARGET, msr);
}
/*
* Punit Initialization code. This all isn't documented, but
* this is the recipe.
@@ -109,6 +136,9 @@ static bool punit_init(void)
uint32_t data;
struct stopwatch sw;
/* Thermal throttle activation offset */
configure_thermal_target();
/*
* Software Core Disable Mask (P_CR_CORE_DISABLE_MASK_0_0_0_MCHBAR).
* Enable all cores here.