superio: Use 'pnp_devfn_t' over 'device_t' in romstage component

The romstage component of Super I/O support is in fact written around passing a lower and upper half packed integer. We currently have two typedef's for this, 'device_t' and 'pnp_devfn_t'. We wish to make use of 'pnp_devfn_t' over 'device_t' as 'device_t' changes it's typedef in the ramstage context and so is really a conflicting definition. This helps solve problems down the road to having the 'real' 'device_t' definition usable in romstage later. This follows on from the rational given in: c2956e7 device/pci_early.c: Mixes up variants of a typedefs to 'u32' Change-Id: Ia9f238ebb944f9fe7b274621ee0c09a6de288a76 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6231 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins)
2014-07-09 20:26:25 +10:00
parent 377fd75493
commit 85836c2215
61 changed files with 162 additions and 162 deletions
--- a/src/superio/ite/common/early_serial.c
+++ b/src/superio/ite/common/early_serial.c
@@ -33,14 +33,14 @@
 #define ITE_CONFIG_REG_WATCHDOG  0x72 /* watchdog config */

 /* Helper procedure */
-static void ite_sio_write(device_t dev, u8 reg, u8 value)
+static void ite_sio_write(pnp_devfn_t dev, u8 reg, u8 value)
 {
 	pnp_set_logical_device(dev);
 	pnp_write_config(dev, reg, value);
 }

 /* Enable configuration */
-static void pnp_enter_conf_state(device_t dev)
+static void pnp_enter_conf_state(pnp_devfn_t dev)
 {
 	u16 port = dev >> 8;

@@ -51,12 +51,12 @@ static void pnp_enter_conf_state(device_t dev)
 }

 /* Disable configuration */
-static void pnp_exit_conf_state(device_t dev)
+static void pnp_exit_conf_state(pnp_devfn_t dev)
 {
 	ite_sio_write(dev, ITE_CONFIG_REG_CC, 0x02);
 }

-void ite_reg_write(device_t dev, u8 reg, u8 value)
+void ite_reg_write(pnp_devfn_t dev, u8 reg, u8 value)
 {
 	pnp_enter_conf_state(dev);
 	ite_sio_write(dev, reg, value);
@@ -71,13 +71,13 @@ void ite_reg_write(device_t dev, u8 reg, u8 value)
 * ITE_UART_CLK_PREDIVIDE_24
 * ITE_UART_CLK_PREDIVIDE_48 (default)
 */
-void ite_conf_clkin(device_t dev, u8 predivide)
+void ite_conf_clkin(pnp_devfn_t dev, u8 predivide)
 {
 	ite_reg_write(dev, ITE_CONFIG_REG_CLOCKSEL, (0x1 & predivide));
 }

 /* Bring up early serial debugging output before the RAM is initialized. */
-void ite_enable_serial(device_t dev, u16 iobase)
+void ite_enable_serial(pnp_devfn_t dev, u16 iobase)
 {
 	pnp_enter_conf_state(dev);
 	pnp_set_logical_device(dev);
@@ -101,7 +101,7 @@ void ite_enable_serial(device_t dev, u16 iobase)
 * and pass: GPIO_DEV
 */

-void ite_enable_3vsbsw(device_t dev)
+void ite_enable_3vsbsw(pnp_devfn_t dev)
 {
 	u8 tmp;
 	pnp_enter_conf_state(dev);
@@ -118,7 +118,7 @@ void ite_enable_3vsbsw(device_t dev)
 * and pass: GPIO_DEV
 */

-void ite_kill_watchdog(device_t dev)
+void ite_kill_watchdog(pnp_devfn_t dev)
 {
 	pnp_enter_conf_state(dev);
 	ite_sio_write(dev, ITE_CONFIG_REG_WATCHDOG, 0x00);
--- a/src/superio/ite/common/ite.h
+++ b/src/superio/ite/common/ite.h
@@ -27,12 +27,12 @@
 #define ITE_UART_CLK_PREDIVIDE_48 0x00 /* default */
 #define ITE_UART_CLK_PREDIVIDE_24 0x01

-void ite_conf_clkin(device_t dev, u8 predivide);
-void ite_enable_serial(device_t dev, u16 iobase);
+void ite_conf_clkin(pnp_devfn_t dev, u8 predivide);
+void ite_enable_serial(pnp_devfn_t dev, u16 iobase);

 /* Some boards need to init wdt+gpio's very early */
-void ite_reg_write(device_t dev, u8 reg, u8 value);
-void ite_enable_3vsbsw(device_t dev);
-void ite_kill_watchdog(device_t dev);
+void ite_reg_write(pnp_devfn_t dev, u8 reg, u8 value);
+void ite_enable_3vsbsw(pnp_devfn_t dev);
+void ite_kill_watchdog(pnp_devfn_t dev);

 #endif /* SUPERIO_ITE_COMMON_ROMSTAGE_H */
--- a/src/superio/ite/it8661f/early_serial.c
+++ b/src/superio/ite/it8661f/early_serial.c
@@ -26,7 +26,7 @@
 /* Base address 0x3f0: 0x86 0x80 0x55 0x55. */
 /* Base address 0x3bd: 0x86 0x80 0x55 0xaa. */
 /* Base address 0x370: 0x86 0x80 0xaa 0x55. */
-static void pnp_enter_ext_func_mode(device_t dev)
+static void pnp_enter_ext_func_mode(pnp_devfn_t dev)
 {
 	int i;
 	u16 port = dev >> 8;
@@ -42,7 +42,7 @@ static void pnp_enter_ext_func_mode(device_t dev)
 		outb(init_values[i], port);
 }

-static void pnp_exit_ext_func_mode(device_t dev)
+static void pnp_exit_ext_func_mode(pnp_devfn_t dev)
 {
 	pnp_write_config(dev, IT8661F_REG_CC, (1 << 1));
 }
@@ -55,21 +55,21 @@ static void pnp_exit_ext_func_mode(device_t dev)
 *
 * Bits: FDC (0), Com1 (1), Com2 (2), PP (3), IR (4). Bits 5-7 are reserved.
 */
-static void it8661f_enable_logical_devices(device_t dev)
+static void it8661f_enable_logical_devices(pnp_devfn_t dev)
 {
 	pnp_enter_ext_func_mode(dev);
 	pnp_write_config(dev, IT8661F_REG_LDE, 0x1f);
 	pnp_exit_ext_func_mode(dev);
 }

-static void it8661f_set_clkin(device_t dev, u8 clkin)
+static void it8661f_set_clkin(pnp_devfn_t dev, u8 clkin)
 {
 	pnp_enter_ext_func_mode(dev);
 	pnp_write_config(dev, IT8661F_REG_SWSUSP, (clkin << 1));
 	pnp_exit_ext_func_mode(dev);
 }

-void it8661f_enable_serial(device_t dev, u16 iobase)
+void it8661f_enable_serial(pnp_devfn_t dev, u16 iobase)
 {
 	pnp_enter_ext_func_mode(dev);
 	pnp_set_logical_device(dev);
--- a/src/superio/ite/it8661f/it8661f.h
+++ b/src/superio/ite/it8661f/it8661f.h
@@ -52,6 +52,6 @@ static const u8 init_values[] = {
 	0xe8, 0x74, 0x3a, 0x9d, /**/ 0xce, 0xe7, 0x73, 0x39,
 };

-void it8661f_enable_serial(device_t dev, u16 iobase);
+void it8661f_enable_serial(pnp_devfn_t dev, u16 iobase);

 #endif /* SUPERIO_ITE_IT8661F_H */
--- a/src/superio/ite/it8671f/early_serial.c
+++ b/src/superio/ite/it8671f/early_serial.c
@@ -89,7 +89,7 @@ void it8671f_48mhz_clkin(void)
 }

 /* Enable the serial port(s). */
-void it8671f_enable_serial(device_t dev, u16 iobase)
+void it8671f_enable_serial(pnp_devfn_t dev, u16 iobase)
 {
 	it8671f_enter_conf();

--- a/src/superio/ite/it8671f/it8671f.h
+++ b/src/superio/ite/it8671f/it8671f.h
@@ -34,6 +34,6 @@
 #define IT8671F_KBCM 0x06 /* PS/2 mouse */

 void it8671f_48mhz_clkin(void);
-void it8671f_enable_serial(device_t dev, u16 iobase);
+void it8671f_enable_serial(pnp_devfn_t dev, u16 iobase);

 #endif /* SUPERIO_ITE_IT8671F__H */
--- a/src/superio/ite/it8718f/early_serial.c
+++ b/src/superio/ite/it8718f/early_serial.c
@@ -27,7 +27,7 @@
 * mechanism. It lives in the GPIO LDN. However, register 0xEF is not
 * mentioned in the IT8718F datasheet so just hardcode it to 0x7E for now.
 */
-void it8718f_disable_reboot(device_t dev)
+void it8718f_disable_reboot(pnp_devfn_t dev)
 {
 	ite_reg_write(dev, 0xEF, 0x7E);
 }
--- a/src/superio/ite/it8718f/it8718f.h
+++ b/src/superio/ite/it8718f/it8718f.h
@@ -35,6 +35,6 @@
 #define IT8718F_GPIO 0x07 /* GPIO */
 #define IT8718F_IR   0x0a /* Consumer IR */

-void it8718f_disable_reboot(device_t dev);
+void it8718f_disable_reboot(pnp_devfn_t dev);

 #endif /* SUPERIO_ITE_IT8718F_H */
--- a/src/superio/ite/it8772f/early_init.c
+++ b/src/superio/ite/it8772f/early_init.c
@@ -26,8 +26,8 @@
 /* NOTICE: This file is deprecated, use ite/common instead */

 /* RAMstage equiv */
-/* u8 pnp_read_config(device_t dev, u8 reg) */
-u8 it8772f_sio_read(device_t dev, u8 reg)
+/* u8 pnp_read_config(pnp_devfn_t dev, u8 reg) */
+u8 it8772f_sio_read(pnp_devfn_t dev, u8 reg)
 {
 	u16 port = dev >> 8;

@@ -36,8 +36,8 @@ u8 it8772f_sio_read(device_t dev, u8 reg)
 }

 /* RAMstage equiv */
-/* void pnp_write_config(device_t dev, u8 reg, u8 value) */
-void it8772f_sio_write(device_t dev, u8 reg, u8 value)
+/* void pnp_write_config(pnp_devfn_t dev, u8 reg, u8 value) */
+void it8772f_sio_write(pnp_devfn_t dev, u8 reg, u8 value)
 {
 	u16 port = dev >> 8;

@@ -45,7 +45,7 @@ void it8772f_sio_write(device_t dev, u8 reg, u8 value)
 	outb(value, port + 1);
 }

-void it8772f_enter_conf(device_t dev)
+void it8772f_enter_conf(pnp_devfn_t dev)
 {
 	u16 port = dev >> 8;

@@ -55,13 +55,13 @@ void it8772f_enter_conf(device_t dev)
 	outb((port == 0x4e) ? 0xaa : 0x55, port);
 }

-void it8772f_exit_conf(device_t dev)
+void it8772f_exit_conf(pnp_devfn_t dev)
 {
 	it8772f_sio_write(dev, IT8772F_CONFIG_REG_CC, 0x02);
 }

 /* Set AC resume to be up to the Southbridge */
-void it8772f_ac_resume_southbridge(device_t dev)
+void it8772f_ac_resume_southbridge(pnp_devfn_t dev)
 {
 	it8772f_enter_conf(dev);
 	it8772f_sio_write(dev, IT8772F_CONFIG_REG_LDN, IT8772F_EC);
@@ -70,7 +70,7 @@ void it8772f_ac_resume_southbridge(device_t dev)
 }

 /* Configure a set of GPIOs */
-void it8772f_gpio_setup(device_t dev, int set, u8 select, u8 polarity,
+void it8772f_gpio_setup(pnp_devfn_t dev, int set, u8 select, u8 polarity,
 			u8 pullup, u8 output, u8 enable)
 {
 	set--; /* Set 1 is offset 0 */
--- a/src/superio/ite/it8772f/it8772f.h
+++ b/src/superio/ite/it8772f/it8772f.h
@@ -106,10 +106,10 @@
 #include <arch/io.h>
 #include <stdint.h>

-u8 it8772f_sio_read(device_t dev, u8 reg);
-void it8772f_sio_write(device_t dev, u8 reg, u8 value);
-void it8772f_ac_resume_southbridge(device_t dev);
-void it8772f_gpio_setup(device_t dev, int set, u8 select, u8 polarity,
+u8 it8772f_sio_read(pnp_devfn_t dev, u8 reg);
+void it8772f_sio_write(pnp_devfn_t dev, u8 reg, u8 value);
+void it8772f_ac_resume_southbridge(pnp_devfn_t dev);
+void it8772f_gpio_setup(pnp_devfn_t dev, int set, u8 select, u8 polarity,
 			u8 pullup, u8 output, u8 enable);

 /* FIXME: should be static so will be removed later.. */
@@ -117,7 +117,7 @@ void it8772f_gpio_setup(device_t dev, int set, u8 select, u8 polarity,
 #define IT8772F_CONFIG_REG_CC        0x02 /* Configure Control (write-only). */
 #define IT8772F_CONFIG_REG_LDN       0x07 /* Logical Device Number. */

-void it8772f_enter_conf(device_t dev);
-void it8772f_exit_conf(device_t dev);
+void it8772f_enter_conf(pnp_devfn_t dev);
+void it8772f_exit_conf(pnp_devfn_t dev);

 #endif /* SUPERIO_ITE_IT8772F_H */