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mb/hp: Add HP EliteBook Folio 9480m

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The code is based on autoport, with necessary modifications.

This laptop uses SMSC MEC1322 embedded controller, but the EC
interface is the same as the EliteBook laptops of previous generations
that use KBC1126 EC. So it still uses ec/hp/kbc1126, but does not need
EC firmware inserted into CBFS. We also need to leave the end of the
OEM flash content untouched, so the default ROM size is set to 12MiB
instead of 16MiB, and we need to modify the IFD when flashing.

Thanks to persmule for providing the laptop and pointing out how to
program the system flash chip of it.

Change-Id: I2328c43cbb1f488aa1d0ddd9116814d971e5d8ae
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45578
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Iru Cai
2020-09-08 19:50:55 +08:00
committed by Patrick Georgi
parent 43cc3c0273
commit 85d0e7611a
18 changed files with 612 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

50
src/mainboard/hp/folio_9480m/Kconfig Normal file
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if BOARD_HP_FOLIO_9480M
config BOARD_SPECIFIC_OPTIONS
def_bool y
# The board has a 16MB flash, but the end of the flash needs
# to be reserved, so we use 12MB as default
select BOARD_ROMSIZE_KB_12288
select EC_HP_KBC1126
select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES
select INTEL_GMA_HAVE_VBT
select INTEL_LYNXPOINT_LP
select MAINBOARD_HAS_LIBGFXINIT
select MAINBOARD_HAS_LPC_TPM
select MAINBOARD_HAS_TPM1
select MAINBOARD_USES_IFD_GBE_REGION
select NORTHBRIDGE_INTEL_HASWELL
select SERIRQ_CONTINUOUS_MODE
select SOUTHBRIDGE_INTEL_LYNXPOINT
select SYSTEM_TYPE_LAPTOP
config MAINBOARD_DIR
string
default "hp/folio_9480m"
config MAINBOARD_PART_NUMBER
string
default "HP EliteBook Folio 9480m"
config VGA_BIOS_FILE
string
default "pci8086,0a16.rom"
config VGA_BIOS_ID
string
default "8086,0a16"
config USBDEBUG_HCD_INDEX
int
default 1
config EC_HP_KBC1126_ECFW_IN_CBFS
bool
default n
config EC_HP_KBC1126_GPE
hex
default 0x6
endif

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src/mainboard/hp/folio_9480m/Kconfig.name Normal file
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config BOARD_HP_FOLIO_9480M
bool "EliteBook Folio 9480m"

2
src/mainboard/hp/folio_9480m/Makefile.inc Normal file
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romstage-y += gpio.c
ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads

3
src/mainboard/hp/folio_9480m/acpi/ec.asl Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
#include <ec/hp/kbc1126/acpi/ec.asl>

14
src/mainboard/hp/folio_9480m/acpi/platform.asl Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
Method(_WAK,1)
{
\_SB.PCI0.LPCB.EC0.ACPI = 1
\_SB.PCI0.LPCB.EC0.SLPT = 0
Return(Package(){0,0})
}
Method(_PTS,1)
{
\_SB.PCI0.LPCB.EC0.SLPT = Arg0
}

3
src/mainboard/hp/folio_9480m/acpi/superio.asl Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
#include <drivers/pc80/pc/ps2_controller.asl>

14
src/mainboard/hp/folio_9480m/acpi_tables.c Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
#include <acpi/acpi_gnvs.h>
#include <southbridge/intel/lynxpoint/nvs.h>
void acpi_create_gnvs(struct global_nvs *gnvs)
{
gnvs->lids = 1;
/* Temperature at which OS will shutdown */
gnvs->tcrt = 100;
/* Temperature at which OS will throttle CPU */
gnvs->tpsv = 90;
}

7
src/mainboard/hp/folio_9480m/board_info.txt Normal file
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Category: laptop
Board URL: https://support.hp.com/us-en/product/hp-elitebook-folio-9480m-notebook-pc/7089926
ROM protocol: SPI
ROM package: SOIC-8
ROM socketed: n
Flashrom support: y
Release year: 2014

BIN
src/mainboard/hp/folio_9480m/data.vbt Normal file
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88
src/mainboard/hp/folio_9480m/devicetree.cb Normal file
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chip northbridge/intel/haswell
register "dq_pins_interleaved" = "true"
register "ec_present" = "true"
register "gfx" = "GMA_STATIC_DISPLAYS(0)"
register "gpu_dp_b_hotplug" = "4"
register "gpu_dp_c_hotplug" = "4"
register "gpu_panel_power_backlight_off_delay" = "1"
register "gpu_panel_power_backlight_on_delay" = "1"
register "gpu_panel_power_cycle_delay" = "6"
register "gpu_panel_power_down_delay" = "500"
register "gpu_panel_power_up_delay" = "2000"
register "gpu_pch_backlight_pwm_hz" = "200"
register "usb_xhci_on_resume" = "true"
device cpu_cluster 0 on
chip cpu/intel/haswell
register "c1_battery" = "2"
register "c2_battery" = "3"
register "c3_battery" = "9"
register "c1_acpower" = "2"
register "c2_acpower" = "3"
register "c3_acpower" = "9"
device lapic 0 on end
device lapic 0xacac off end
end
end
device domain 0x0 on
subsystemid 0x103c 0x22da inherit
device pci 00.0 on end # Host bridge
device pci 02.0 on end # Internal graphics VGA controller
device pci 03.0 on end # Mini-HD audio
chip southbridge/intel/lynxpoint # Intel Series 8 Lynx Point PCH
register "gen1_dec" = "0x007c0201"
register "gen2_dec" = "0x000c0101"
register "gen4_dec" = "0x000402e9"
register "xhci_default" = "1"
register "sata_ahci" = "1"
register "sata_port1_gen3_dtle" = "0x6"
# SATA(1), M.2(3)
register "sata_port_map" = "0xa"
device pci 13.0 off end # Intel Smart Sound DSP
device pci 14.0 on end # xHCI Controller
device pci 15.0 off end # Serial I/O DMA
device pci 15.1 off end # I2C0
device pci 15.2 off end # I2C1
device pci 15.3 off end # GSPI0
device pci 15.4 off end # GSPI1
device pci 15.5 off end # UART0
device pci 15.6 off end # UART1
device pci 16.0 on end # Management Engine Interface 1
device pci 16.1 off end # Management Engine Interface 2
device pci 16.2 off end # Management Engine IDE-R
device pci 16.3 off end # Management Engine KT
device pci 17.0 off end # SDIO
device pci 19.0 on end # Intel Gigabit Ethernet
device pci 1b.0 on end # High Definition Audio
device pci 1c.0 on end # PCIe Port #1
device pci 1c.1 on end # PCIe Port #2, Realtek Card Reader
device pci 1c.2 off end # PCIe Port #3
device pci 1c.3 on # PCIe Port #4, WLAN
smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther"
"M.2 2230" "SlotDataBusWidth1X"
end
device pci 1c.4 off end # PCIe Port #5
device pci 1c.5 off end # PCIe Port #6
device pci 1d.0 on end # USB2 EHCI #1
device pci 1f.0 on # LPC bridge
chip drivers/pc80/tpm
device pnp 0c31.0 on end
end
# This laptop uses MEC1322, but it has the same interface
# as the KBC1126 laptops
chip ec/hp/kbc1126
register "ec_data_port" = "0x62"
register "ec_cmd_port" = "0x66"
register "ec_ctrl_reg" = "0x81"
register "ec_fan_ctrl_value" = "0x6b"
device pnp ff.1 off end
end
end
device pci 1f.2 on end # SATA Controller (AHCI)
device pci 1f.3 on end # SMBus
device pci 1f.6 off end # Thermal
end
end
end

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src/mainboard/hp/folio_9480m/dsdt.asl Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
#include <acpi/acpi.h>
DefinitionBlock(
"dsdt.aml",
"DSDT",
ACPI_DSDT_REV_2,
OEM_ID,
ACPI_TABLE_CREATOR,
0x20141018 /* OEM revision */
)
{
#include "acpi/platform.asl"
#include <cpu/intel/common/acpi/cpu.asl>
#include <southbridge/intel/common/acpi/platform.asl>
/* global NVS and variables. */
#include <southbridge/intel/lynxpoint/acpi/globalnvs.asl>
#include <southbridge/intel/common/acpi/sleepstates.asl>
Device (\_SB.PCI0)
{
#include <northbridge/intel/haswell/acpi/haswell.asl>
#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
#include <southbridge/intel/lynxpoint/acpi/pch.asl>
}
}

18
src/mainboard/hp/folio_9480m/gma-mainboard.ads Normal file
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-- SPDX-License-Identifier: GPL-2.0-or-later
with HW.GFX.GMA;
with HW.GFX.GMA.Display_Probing;
use HW.GFX.GMA;
use HW.GFX.GMA.Display_Probing;
private package GMA.Mainboard is
ports : constant Port_List :=
(DP1, -- DP1/HDMI1: DisplayPorts on board and dock
HDMI1,
DP2, -- DP2: VGA ports on board and dock
eDP,
others => Disabled);
end GMA.Mainboard;

108
src/mainboard/hp/folio_9480m/gpio.c Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
#include <southbridge/intel/lynxpoint/lp_gpio.h>
const struct pch_lp_gpio_map mainboard_gpio_map[] = {
[0] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL },
[1] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL },
[2] = LP_GPIO_OUT_LOW,
[3] = LP_GPIO_OUT_HIGH,
[4] = LP_GPIO_OUT_HIGH,
[5] = LP_GPIO_OUT_HIGH,
[6] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL },
[7] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL },
[8] = LP_GPIO_OUT_HIGH,
[9] = LP_GPIO_OUT_HIGH,
[10] = LP_GPIO_OUT_HIGH,
[11] = LP_GPIO_OUT_HIGH,
[12] = LP_GPIO_NATIVE,
[13] = LP_GPIO_OUT_HIGH,
[14] = LP_GPIO_OUT_HIGH,
[15] = LP_GPIO_OUT_HIGH,
[16] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL,
.route = GPIO_ROUTE_SMI },
[17] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL },
[18] = LP_GPIO_OUT_HIGH,
[19] = LP_GPIO_NATIVE,
[20] = LP_GPIO_NATIVE,
[21] = LP_GPIO_NATIVE,
[22] = LP_GPIO_OUT_HIGH,
[23] = LP_GPIO_OUT_HIGH,
[24] = LP_GPIO_OUT_HIGH,
[25] = LP_GPIO_OUT_HIGH,
[26] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL },
[27] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL },
[28] = LP_GPIO_OUT_HIGH,
[29] = LP_GPIO_OUT_HIGH,
[30] = LP_GPIO_NATIVE,
[31] = LP_GPIO_NATIVE,
[32] = LP_GPIO_NATIVE,
[33] = LP_GPIO_NATIVE,
[34] = LP_GPIO_OUT_HIGH,
[35] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL },
[36] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL,
.route = GPIO_ROUTE_SMI },
[37] = LP_GPIO_NATIVE,
[38] = LP_GPIO_NATIVE,
[39] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL,
.route = GPIO_ROUTE_SMI },
[40] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL,
.route = GPIO_ROUTE_SMI },
[41] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL },
[42] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL },
[43] = LP_GPIO_OUT_HIGH,
[44] = LP_GPIO_OUT_LOW,
[45] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL },
[46] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL },
[47] = LP_GPIO_OUT_HIGH,
[48] = LP_GPIO_OUT_LOW,
[49] = LP_GPIO_OUT_HIGH,
[50] = LP_GPIO_OUT_HIGH,
[51] = LP_GPIO_OUT_HIGH,
[52] = LP_GPIO_OUT_HIGH,
[53] = LP_GPIO_OUT_HIGH,
[54] = LP_GPIO_OUT_LOW,
[55] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL,
.pirq = GPIO_PIRQ_APIC_ROUTE },
[56] = LP_GPIO_OUT_HIGH,
[57] = LP_GPIO_OUT_LOW,
[58] = LP_GPIO_OUT_HIGH,
[59] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL },
[60] = LP_GPIO_OUT_HIGH,
[61] = LP_GPIO_OUT_LOW,
[62] = LP_GPIO_NATIVE,
[63] = LP_GPIO_NATIVE,
[64] = LP_GPIO_OUT_HIGH,
[65] = LP_GPIO_OUT_LOW,
[66] = LP_GPIO_OUT_HIGH,
[67] = LP_GPIO_OUT_HIGH,
[68] = LP_GPIO_OUT_HIGH,
[69] = LP_GPIO_OUT_HIGH,
[70] = LP_GPIO_OUT_LOW,
[71] = LP_GPIO_NATIVE,
[72] = LP_GPIO_NATIVE,
[73] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL },
[74] = LP_GPIO_NATIVE,
[75] = LP_GPIO_NATIVE,
[76] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL },
[77] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL },
[78] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL,
.route = GPIO_ROUTE_SMI },
[79] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL },
[80] = LP_GPIO_OUT_LOW,
[81] = LP_GPIO_NATIVE,
[82] = LP_GPIO_OUT_HIGH,
[83] = LP_GPIO_OUT_HIGH,
[84] = LP_GPIO_OUT_HIGH,
[85] = LP_GPIO_OUT_HIGH,
[86] = LP_GPIO_OUT_HIGH,
[87] = LP_GPIO_OUT_HIGH,
[88] = LP_GPIO_OUT_HIGH,
[89] = LP_GPIO_OUT_HIGH,
[90] = LP_GPIO_OUT_HIGH,
[91] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL },
[92] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL },
[93] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL },
[94] = LP_GPIO_OUT_HIGH,
LP_GPIO_END
};

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src/mainboard/hp/folio_9480m/hda_verb.c Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
#include <device/azalia_device.h>
const u32 cim_verb_data[] = {
0x10ec0280, /* Codec Vendor / Device ID: Realtek */
0x103c22db, /* Subsystem ID */
57, /* Number of 4 dword sets */
AZALIA_SUBVENDOR(0, 0x103c22db),
AZALIA_RESET(1),
AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
AZALIA_PIN_CFG(0, 0x13, 0x40000000),
AZALIA_PIN_CFG(0, 0x14, 0x90170110),
AZALIA_PIN_CFG(0, 0x15, 0x0321101f),
AZALIA_PIN_CFG(0, 0x16, 0x411111f0),
AZALIA_PIN_CFG(0, 0x17, 0x411111f0),
AZALIA_PIN_CFG(0, 0x18, 0x411111f0),
AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
AZALIA_PIN_CFG(0, 0x1a, 0x03a11020),
AZALIA_PIN_CFG(0, 0x1b, 0x411111f0),
AZALIA_PIN_CFG(0, 0x1d, 0x40738105),
AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),
/* The following is from the OEM firmware */
0x02050007, 0x0204c200, 0x02050063, 0x02044800,
0x02050066, 0x02040809, 0x02050015, 0x02048842,
0x0205000f, 0x0204cccc, 0x02050010, 0x0204ccdd,
0x02050065, 0x02042000, 0x0205001c, 0x0204c900,
0x02050018, 0x02043788, 0x02050008, 0x02048210,
0x02050068, 0x02043022, 0x02050006, 0x02040800,
0x02050061, 0x02040403, 0x02050061, 0x02040403,
0x0205005f, 0x02040800, 0x02050060, 0x02040800,
0x0205002c, 0x02044002, 0x0205002e, 0x02041ec4,
0x0205002f, 0x02040000, 0x02050033, 0x0204c5e8,
0x02050034, 0x02041a98, 0x02050035, 0x0204f5ad,
0x02050036, 0x0204cbd2, 0x02050037, 0x02041605,
0x02050038, 0x0204f5ad, 0x02050039, 0x0204ea5f,
0x0205003a, 0x02040b42, 0x0205003b, 0x0204fb54,
0x0205003c, 0x0204fcd9, 0x0205003d, 0x02040000,
0x02050030, 0x02041f5c, 0x02050031, 0x02040111,
0x02050032, 0x02041f5f, 0x0205003e, 0x02041ea9,
0x0205002f, 0x02040000, 0x02050042, 0x0204c66e,
0x02050043, 0x02041a29, 0x02050035, 0x0204f5ad,
0x02050044, 0x0204ccdd, 0x02050045, 0x02041549,
0x02050038, 0x0204f5ad, 0x02050046, 0x0204ee79,
0x02050047, 0x020409f4, 0x0205003b, 0x0204fb54,
0x02050048, 0x0204fa4c, 0x0205003d, 0x02040000,
0x0205003f, 0x02041f4d, 0x02050040, 0x02040129,
0x02050041, 0x02041f51, 0x02050049, 0x02041f61,
0x0205002f, 0x02040000, 0x0205004d, 0x0204c2f4,
0x0205004e, 0x02041d2e, 0x02050035, 0x0204f5ad,
0x0205004f, 0x0204c5e8, 0x02050050, 0x02041a98,
0x02050038, 0x0204f5ad, 0x02050051, 0x0204d30e,
0x02050052, 0x020413e6, 0x0205003b, 0x0204fb54,
0x02050053, 0x02040b73, 0x0205003d, 0x02040000,
0x0205004a, 0x02041faf, 0x0205004b, 0x0204008a,
0x0205004c, 0x02041fb0, 0x02050054, 0x02041fb0,
0x0205002f, 0x02040000, 0x02050058, 0x0204c17a,
0x02050059, 0x02041e8f, 0x02050035, 0x0204f5ad,
0x0205005a, 0x0204c2f4, 0x0205005b, 0x02041d2e,
0x02050038, 0x0204f5ad, 0x0205005c, 0x0204c899,
0x0205005d, 0x0204195b, 0x0205003b, 0x0204fb54,
0x0205005e, 0x02041444, 0x0205003d, 0x02040000,
0x02050055, 0x02041fd8, 0x02050056, 0x02040045,
0x02050057, 0x02041fd8, 0x0205002c, 0x0204ffc2,
0x02050026, 0x02042828, 0x02050029, 0x02040250,
0x02050004, 0x0204c09e, 0x0205000e, 0x02045001,
};
const u32 pc_beep_verbs[0] = {};
AZALIA_ARRAY_SIZES;

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src/mainboard/hp/folio_9480m/romstage.c Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
#include <stdint.h>
#include <northbridge/intel/haswell/haswell.h>
#include <northbridge/intel/haswell/raminit.h>
#include <southbridge/intel/lynxpoint/pch.h>
void mainboard_config_rcba(void)
{
RCBA16(D31IR) = DIR_ROUTE(PIRQF, PIRQD, PIRQC, PIRQA);
RCBA16(D29IR) = DIR_ROUTE(PIRQB, PIRQD, PIRQA, PIRQC);
RCBA16(D28IR) = DIR_ROUTE(PIRQA, PIRQA, PIRQA, PIRQA);
RCBA16(D27IR) = DIR_ROUTE(PIRQG, PIRQB, PIRQC, PIRQD);
RCBA16(D26IR) = DIR_ROUTE(PIRQA, PIRQF, PIRQC, PIRQD);
RCBA16(D25IR) = DIR_ROUTE(PIRQE, PIRQB, PIRQC, PIRQD);
RCBA16(D22IR) = DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD);
RCBA16(D20IR) = DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD);
}
void mb_get_spd_map(uint8_t spd_map[4])
{
spd_map[0] = 0xa0;
spd_map[2] = 0xa4;
}
void mainboard_fill_pei_data(struct pei_data *pei_data)
{
struct usb2_port_setting usb2_ports[MAX_USB2_PORTS] = {
/* Length, Enable, OCn#, Location */
{ 0x0080, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, /* dock */
{ 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, /* left, EHCI debug */
{ 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, /* right */
{ 0x0080, 1, USB_OC_PIN_SKIP, USB_PORT_MINI_PCIE }, /* WLAN */
{ 0x0110, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, /* SmartCard */
{ 0x0080, 1, USB_OC_PIN_SKIP, USB_PORT_MINI_PCIE }, /* WWAN */
{ 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, /* Webcam */
{ 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL },
};
struct usb3_port_setting usb3_ports[MAX_USB3_PORTS] = {
{ 1, USB_OC_PIN_SKIP }, /* dock */
{ 1, USB_OC_PIN_SKIP }, /* left */
{ 1, USB_OC_PIN_SKIP }, /* right */
{ 0, USB_OC_PIN_SKIP },
};
memcpy(pei_data->usb2_ports, usb2_ports, sizeof(usb2_ports));
memcpy(pei_data->usb3_ports, usb3_ports, sizeof(usb3_ports));
}