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cpu/mtrr.h: Fix macro names for MTRR registers

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We use UNDERSCORE_CASE. For the MTRR macros that refer to an MSR,
we also remove the _MSR suffix, as they are, by definition, MSRs.

Change-Id: Id4483a75d62cf1b478a9105ee98a8f55140ce0ef
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/11761
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
This commit is contained in:
Alexandru Gagniuc
2015-09-30 20:23:09 -07:00
parent 58562405c8
commit 86091f94b6
47 changed files with 490 additions and 493 deletions
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12
src/cpu/intel/haswell/smmrelocate.c
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@@ -73,8 +73,8 @@ static inline void write_smrr(struct smm_relocation_params *relo_params)
{
printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n",
relo_params->smrr_base.lo, relo_params->smrr_mask.lo);
wrmsr(SMRRphysBase_MSR, relo_params->smrr_base);
wrmsr(SMRRphysMask_MSR, relo_params->smrr_mask);
wrmsr(SMRR_PHYS_BASE, relo_params->smrr_base);
wrmsr(SMRR_PHYS_MASK, relo_params->smrr_mask);
}
static inline void write_emrr(struct smm_relocation_params *relo_params)
@@ -214,7 +214,7 @@ static void asmlinkage cpu_smm_do_relocation(void *arg)
update_save_state(cpu, relo_params, runtime);
/* Write EMRR and SMRR MSRs based on indicated support. */
mtrr_cap = rdmsr(MTRRcap_MSR);
mtrr_cap = rdmsr(MTRR_CAP_MSR);
if (mtrr_cap.lo & SMRR_SUPPORTED)
write_smrr(relo_params);
@@ -272,7 +272,7 @@ static void fill_in_relocation_params(struct device *dev,
/* SMRR has 32-bits of valid address aligned to 4KiB. */
params->smrr_base.lo = (params->smram_base & rmask) | MTRR_TYPE_WRBACK;
params->smrr_base.hi = 0;
params->smrr_mask.lo = (~(tseg_size - 1) & rmask) | MTRRphysMaskValid;
params->smrr_mask.lo = (~(tseg_size - 1) & rmask) | MTRR_PHYS_MASK_VALID;
params->smrr_mask.hi = 0;
/* The EMRR and UNCORE_EMRR are at IEDBASE + 2MiB */
@@ -283,14 +283,14 @@ static void fill_in_relocation_params(struct device *dev,
* on the number of physical address bits supported. */
params->emrr_base.lo = emrr_base | MTRR_TYPE_WRBACK;
params->emrr_base.hi = 0;
params->emrr_mask.lo = (~(emrr_size - 1) & rmask) | MTRRphysMaskValid;
params->emrr_mask.lo = (~(emrr_size - 1) & rmask) | MTRR_PHYS_MASK_VALID;
params->emrr_mask.hi = (1 << (phys_bits - 32)) - 1;
/* UNCORE_EMRR has 39 bits of valid address aligned to 4KiB. */
params->uncore_emrr_base.lo = emrr_base;
params->uncore_emrr_base.hi = 0;
params->uncore_emrr_mask.lo = (~(emrr_size - 1) & rmask) |
MTRRphysMaskValid;
MTRR_PHYS_MASK_VALID;
params->uncore_emrr_mask.hi = (1 << (39 - 32)) - 1;
}