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cpu/mtrr.h: Fix macro names for MTRR registers

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We use UNDERSCORE_CASE. For the MTRR macros that refer to an MSR,
we also remove the _MSR suffix, as they are, by definition, MSRs.

Change-Id: Id4483a75d62cf1b478a9105ee98a8f55140ce0ef
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/11761
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
This commit is contained in:
Alexandru Gagniuc
2015-09-30 20:23:09 -07:00
parent 58562405c8
commit 86091f94b6
47 changed files with 490 additions and 493 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
src/cpu/intel/model_2065x/bootblock.c
View File

@@ -43,10 +43,10 @@ static void set_var_mtrr(
msr_t basem, maskm;
basem.lo = base | type;
basem.hi = 0;
wrmsr(MTRRphysBase_MSR(reg), basem);
maskm.lo = ~(size - 1) | MTRRphysMaskValid;
wrmsr(MTRR_PHYS_BASE(reg), basem);
maskm.lo = ~(size - 1) | MTRR_PHYS_MASK_VALID;
maskm.hi = (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1;
wrmsr(MTRRphysMask_MSR(reg), maskm);
wrmsr(MTRR_PHYS_MASK(reg), maskm);
}
static void enable_rom_caching(void)
@@ -60,7 +60,7 @@ static void enable_rom_caching(void)
/* Enable Variable MTRRs */
msr.hi = 0x00000000;
msr.lo = 0x00000800;
wrmsr(MTRRdefType_MSR, msr);
wrmsr(MTRR_DEF_TYPE_MSR, msr);
}
static void set_flex_ratio_to_tdp_nominal(void)

42
src/cpu/intel/model_2065x/cache_as_ram.inc
View File

@@ -48,8 +48,8 @@ wait_for_sipi:
jc wait_for_sipi
post_code(0x21)
/* Clean-up MTRRdefType_MSR. */
movl $MTRRdefType_MSR, %ecx
/* Clean-up MTRR_DEF_TYPE_MSR. */
movl $MTRR_DEF_TYPE_MSR, %ecx
xorl %eax, %eax
xorl %edx, %edx
wrmsr
@@ -69,7 +69,7 @@ clear_mtrrs:
jnz clear_mtrrs
/* Zero out all variable range MTRRs. */
movl $MTRRcap_MSR, %ecx
movl $MTRR_CAP_MSR, %ecx
rdmsr
andl $0xff, %eax
shl $1, %eax
@@ -85,24 +85,24 @@ clear_var_mtrrs:
post_code(0x23)
/* Set Cache-as-RAM base address. */
movl $(MTRRphysBase_MSR(0)), %ecx
movl $(MTRR_PHYS_BASE(0)), %ecx
movl $(CACHE_AS_RAM_BASE | MTRR_TYPE_WRBACK), %eax
xorl %edx, %edx
wrmsr
post_code(0x24)
/* Set Cache-as-RAM mask. */
movl $(MTRRphysMask_MSR(0)), %ecx
movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRRphysMaskValid), %eax
movl $(MTRR_PHYS_MASK(0)), %ecx
movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax
movl $CPU_PHYSMASK_HI, %edx
wrmsr
post_code(0x25)
/* Enable MTRR. */
movl $MTRRdefType_MSR, %ecx
movl $MTRR_DEF_TYPE_MSR, %ecx
rdmsr
orl $MTRRdefTypeEn, %eax
orl $MTRR_DEF_TYPE_EN, %eax
wrmsr
/* Enable cache (CR0.CD = 0, CR0.NW = 0). */
@@ -139,7 +139,7 @@ clear_var_mtrrs:
movl %eax, %cr0
/* Enable cache for our code in Flash because we do XIP here */
movl $MTRRphysBase_MSR(1), %ecx
movl $MTRR_PHYS_BASE(1), %ecx
xorl %edx, %edx
/*
* IMPORTANT: The following calculation _must_ be done at runtime. See
@@ -150,9 +150,9 @@ clear_var_mtrrs:
orl $MTRR_TYPE_WRPROT, %eax
wrmsr
movl $MTRRphysMask_MSR(1), %ecx
movl $MTRR_PHYS_MASK(1), %ecx
movl $CPU_PHYSMASK_HI, %edx
movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax
movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax
wrmsr
post_code(0x27)
@@ -189,9 +189,9 @@ before_romstage:
post_code(0x31)
/* Disable MTRR. */
movl $MTRRdefType_MSR, %ecx
movl $MTRR_DEF_TYPE_MSR, %ecx
rdmsr
andl $(~MTRRdefTypeEn), %eax
andl $(~MTRR_DEF_TYPE_EN), %eax
wrmsr
post_code(0x31)
@@ -228,12 +228,12 @@ before_romstage:
/* Enable Write Back and Speculative Reads for the first MB
* and ramstage.
*/
movl $MTRRphysBase_MSR(0), %ecx
movl $MTRR_PHYS_BASE(0), %ecx
movl $(0x00000000 | MTRR_TYPE_WRBACK), %eax
xorl %edx, %edx
wrmsr
movl $MTRRphysMask_MSR(0), %ecx
movl $(~(CONFIG_RAMTOP - 1) | MTRRphysMaskValid), %eax
movl $MTRR_PHYS_MASK(0), %ecx
movl $(~(CONFIG_RAMTOP - 1) | MTRR_PHYS_MASK_VALID), %eax
movl $CPU_PHYSMASK_HI, %edx // 36bit address space
wrmsr
@@ -241,12 +241,12 @@ before_romstage:
/* Enable Caching and speculative Reads for the
* complete ROM now that we actually have RAM.
*/
movl $MTRRphysBase_MSR(1), %ecx
movl $MTRR_PHYS_BASE(1), %ecx
movl $(CACHE_ROM_BASE | MTRR_TYPE_WRPROT), %eax
xorl %edx, %edx
wrmsr
movl $MTRRphysMask_MSR(1), %ecx
movl $(~(CACHE_ROM_SIZE - 1) | MTRRphysMaskValid), %eax
movl $MTRR_PHYS_MASK(1), %ecx
movl $(~(CACHE_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax
movl $CPU_PHYSMASK_HI, %edx
wrmsr
#endif
@@ -261,9 +261,9 @@ before_romstage:
post_code(0x3a)
/* Enable MTRR. */
movl $MTRRdefType_MSR, %ecx
movl $MTRR_DEF_TYPE_MSR, %ecx
rdmsr
orl $MTRRdefTypeEn, %eax
orl $MTRR_DEF_TYPE_EN, %eax
wrmsr
post_code(0x3b)