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cpu/mtrr.h: Fix macro names for MTRR registers

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We use UNDERSCORE_CASE. For the MTRR macros that refer to an MSR,
we also remove the _MSR suffix, as they are, by definition, MSRs.

Change-Id: Id4483a75d62cf1b478a9105ee98a8f55140ce0ef
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/11761
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
This commit is contained in:
Alexandru Gagniuc
2015-09-30 20:23:09 -07:00
parent 58562405c8
commit 86091f94b6
47 changed files with 490 additions and 493 deletions
Download Patch File Download Diff File Expand all files Collapse all files

14
src/soc/intel/skylake/bootblock/cpu.c
View File

@@ -45,10 +45,10 @@ static void set_var_mtrr(
msr_t basem, maskm;
basem.lo = base | type;
basem.hi = 0;
wrmsr(MTRRphysBase_MSR(reg), basem);
maskm.lo = ~(size - 1) | MTRRphysMaskValid;
wrmsr(MTRR_PHYS_BASE(reg), basem);
maskm.lo = ~(size - 1) | MTRR_PHYS_MASK_VALID;
maskm.hi = (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1;
wrmsr(MTRRphysMask_MSR(reg), maskm);
wrmsr(MTRR_PHYS_MASK(reg), maskm);
}
static void enable_rom_caching(void)
@@ -62,7 +62,7 @@ static void enable_rom_caching(void)
/* Enable Variable MTRRs */
msr.hi = 0x00000000;
msr.lo = 0x00000800;
wrmsr(MTRRdefType_MSR, msr);
wrmsr(MTRR_DEF_TYPE_MSR, msr);
}
static void bootblock_mdelay(int ms)
@@ -164,14 +164,14 @@ static void set_flex_ratio_to_tdp_nominal(void)
static void check_for_clean_reset(void)
{
msr_t msr;
msr = rdmsr(MTRRdefType_MSR);
msr = rdmsr(MTRR_DEF_TYPE_MSR);
/*
* Use the MTRR default type MSR as a proxy for detecting INIT#.
* Reset the system if any known bits are set in that MSR. That is
* an indication of the CPU not being properly reset.
*/
if (msr.lo & (MTRRdefTypeEn | MTRRdefTypeFixEn))
if (msr.lo & (MTRR_DEF_TYPE_EN | MTRR_DEF_TYPE_FIX_EN))
soft_reset();
}
@@ -191,7 +191,7 @@ static void patch_microcode(void)
* MTRRCAP[12]. Check for this feature and avoid reloading the
* same microcode during early cpu initialization.
*/
msr = rdmsr(MTRRcap_MSR);
msr = rdmsr(MTRR_CAP_MSR);
if ((msr.lo & PRMRR_SUPPORTED) && (current_rev != patch->rev - 1))
intel_update_microcode_from_cbfs();
}

2
src/soc/intel/skylake/cpu.c
View File

@@ -467,6 +467,6 @@ int soc_skip_ucode_update(u32 current_patch_id, u32 new_patch_id)
* MTRRCAP[12]. Check for this feature and avoid reloading the
* same microcode during cpu initialization.
*/
msr = rdmsr(MTRRcap_MSR);
msr = rdmsr(MTRR_CAP_MSR);
return (msr.lo & PRMRR_SUPPORTED) && (current_patch_id == new_patch_id - 1);
}

2
src/soc/intel/skylake/include/soc/msr.h
View File

@@ -103,7 +103,7 @@
#define SMBASE_MSR 0xc20
#define IEDBASE_MSR 0xc22
/* MTRRcap_MSR bits */
/* MTRR_CAP_MSR bits */
#define SMRR_SUPPORTED (1<<11)
#define PRMRR_SUPPORTED (1<<12)

12
src/soc/intel/skylake/smmrelocate.c
View File

@@ -44,8 +44,8 @@ static inline void write_smrr(struct smm_relocation_params *relo_params)
{
printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n",
relo_params->smrr_base.lo, relo_params->smrr_mask.lo);
wrmsr(SMRRphysBase_MSR, relo_params->smrr_base);
wrmsr(SMRRphysMask_MSR, relo_params->smrr_mask);
wrmsr(SMRR_PHYS_BASE, relo_params->smrr_base);
wrmsr(SMRR_PHYS_MASK, relo_params->smrr_mask);
}
static inline void write_uncore_emrr(struct smm_relocation_params *relo_params)
@@ -191,7 +191,7 @@ static void asmlinkage cpu_smm_do_relocation(void *arg)
update_save_state(cpu, relo_params, runtime);
/* Write EMRR and SMRR MSRs based on indicated support. */
mtrr_cap = rdmsr(MTRRcap_MSR);
mtrr_cap = rdmsr(MTRR_CAP_MSR);
if (mtrr_cap.lo & SMRR_SUPPORTED)
write_smrr(relo_params);
}
@@ -230,7 +230,7 @@ static void fill_in_relocation_params(device_t dev,
/* SMRR has 32-bits of valid address aligned to 4KiB. */
params->smrr_base.lo = (params->smram_base & rmask) | MTRR_TYPE_WRBACK;
params->smrr_base.hi = 0;
params->smrr_mask.lo = (~(tseg_size - 1) & rmask) | MTRRphysMaskValid;
params->smrr_mask.lo = (~(tseg_size - 1) & rmask) | MTRR_PHYS_MASK_VALID;
params->smrr_mask.hi = 0;
/* The EMRR and UNCORE_EMRR are at IEDBASE + 2MiB */
@@ -243,14 +243,14 @@ static void fill_in_relocation_params(device_t dev,
*/
params->emrr_base.lo = emrr_base | MTRR_TYPE_WRBACK;
params->emrr_base.hi = 0;
params->emrr_mask.lo = (~(emrr_size - 1) & rmask) | MTRRphysMaskValid;
params->emrr_mask.lo = (~(emrr_size - 1) & rmask) | MTRR_PHYS_MASK_VALID;
params->emrr_mask.hi = (1 << (phys_bits - 32)) - 1;
/* UNCORE_EMRR has 39 bits of valid address aligned to 4KiB. */
params->uncore_emrr_base.lo = emrr_base;
params->uncore_emrr_base.hi = 0;
params->uncore_emrr_mask.lo = (~(emrr_size - 1) & rmask) |
MTRRphysMaskValid;
MTRR_PHYS_MASK_VALID;
params->uncore_emrr_mask.hi = (1 << (39 - 32)) - 1;
}