sravan/system76-coreboot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

src/soc/intel: Add support for CAR_HAS_SF_MASKS and select for TGL

Browse Source 
Program IA32_CR_SF_QOS_MASK_x MSRs under CAR_HAS_SF_MASKS config
option. Select CAR_HAS_SF_MASKS for Tigerlake.

During CAR teardown code, MSRs IA32_L3_MASK_x & IA32_CR_SF_QOS_MASK_x
are not being reset to default as
per the doc NEM-Enhanced-Mode-Whitepaper-Tigerlake-draft-WW46.5.
Resetting the value of IA32_PQR_ASSOC[32:33] to 00b is sufficient.

Bug=b:171601324
BRANCH=volteer
Test=Build and boot to ChromeOS on Delbin.

Signed-off-by: Shreesh Chhabbi <shreesh.chhabbi@intel.corp-partner.google.com>
Change-Id: Iabf7f387fb5887aca10158788599452c3f2df7e8
Signed-off-by: Shreesh Chhabbi <shreesh.chhabbi@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48286
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Shreesh Chhabbi
2020-12-03 15:06:20 -08:00
committed by Furquan Shaikh
parent 87c7ec7c06
commit 860c68449d
3 changed files with 30 additions and 4 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
src/soc/intel/tigerlake/Kconfig
View File

@@ -25,6 +25,7 @@ config CPU_SPECIFIC_OPTIONS
select HAVE_SMI_HANDLER
select IDT_IN_EVERY_STAGE
select INTEL_CAR_NEM_ENHANCED if !INTEL_CAR_NEM
select CAR_HAS_SF_MASKS if INTEL_CAR_NEM_ENHANCED
select COS_MAPPED_TO_MSB if INTEL_CAR_NEM_ENHANCED
select INTEL_GMA_ACPI
select INTEL_GMA_ADD_VBT if RUN_FSP_GOP