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Lower the RAM init delays we use on the Intel 440BX.

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As per JEDEC, we should wait 200us until voltages and clocks are stable.
Then apply NOPs for 200 clock cycles (for simplicity we use 200us here).

All other delays are so low that we get away with just waiting 1us.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Peter Stuge <peter@stuge.se>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2702 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Uwe Hermann
2007-05-28 14:37:06 +00:00
parent f5a6fd253c
commit 861f964037
1 changed files with 9 additions and 12 deletions
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21
src/northbridge/intel/i440bx/raminit.c
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@@ -509,44 +509,41 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
{ {
int i; int i;
/* TODO: Use a delay here? Needed? */ /* 0. Wait until power/voltages and clocks are stable (200us). */
mdelay(200); udelay(200);
/* TODO: How long should the delays be? Fix later. */ /* 1. Apply NOP. Wait 200 clock cycles (200us should do). */
/* 1. Apply NOP. */
PRINT_DEBUG("RAM Enable 1: Apply NOP\r\n"); PRINT_DEBUG("RAM Enable 1: Apply NOP\r\n");
do_ram_command(ctrl, RAM_COMMAND_NOP, 0); do_ram_command(ctrl, RAM_COMMAND_NOP, 0);
mdelay(10); udelay(200);
/* 2. Precharge all. Wait tRP. */ /* 2. Precharge all. Wait tRP. */
PRINT_DEBUG("RAM Enable 2: Precharge all\r\n"); PRINT_DEBUG("RAM Enable 2: Precharge all\r\n");
do_ram_command(ctrl, RAM_COMMAND_PRECHARGE, 0); do_ram_command(ctrl, RAM_COMMAND_PRECHARGE, 0);
mdelay(10); udelay(1);
/* 3. Perform 8 refresh cycles. Wait tRC each time. */ /* 3. Perform 8 refresh cycles. Wait tRC each time. */
PRINT_DEBUG("RAM Enable 3: CBR\r\n"); PRINT_DEBUG("RAM Enable 3: CBR\r\n");
for (i = 0; i < 8; i++) { for (i = 0; i < 8; i++) {
do_ram_command(ctrl, RAM_COMMAND_CBR, 0); do_ram_command(ctrl, RAM_COMMAND_CBR, 0);
mdelay(10); udelay(1);
} }
/* 4. Mode register set. Wait two memory cycles. */ /* 4. Mode register set. Wait two memory cycles. */
PRINT_DEBUG("RAM Enable 4: Mode register set\r\n"); PRINT_DEBUG("RAM Enable 4: Mode register set\r\n");
do_ram_command(ctrl, RAM_COMMAND_MRS, 0x1d0); do_ram_command(ctrl, RAM_COMMAND_MRS, 0x1d0);
mdelay(10); udelay(2);
mdelay(10);
/* 5. Normal operation. */ /* 5. Normal operation. */
PRINT_DEBUG("RAM Enable 5: Normal operation\r\n"); PRINT_DEBUG("RAM Enable 5: Normal operation\r\n");
do_ram_command(ctrl, RAM_COMMAND_NORMAL, 0); do_ram_command(ctrl, RAM_COMMAND_NORMAL, 0);
mdelay(10); udelay(1);
/* 6. Finally enable refresh. */ /* 6. Finally enable refresh. */
PRINT_DEBUG("RAM Enable 6: Enable refresh\r\n"); PRINT_DEBUG("RAM Enable 6: Enable refresh\r\n");
// pci_write_config8(ctrl->d0, PMCR, 0x10); // pci_write_config8(ctrl->d0, PMCR, 0x10);
spd_enable_refresh(ctrl); spd_enable_refresh(ctrl);
mdelay(10); udelay(1);
PRINT_DEBUG("Northbridge following SDRAM init:\r\n"); PRINT_DEBUG("Northbridge following SDRAM init:\r\n");
DUMPNORTH(); DUMPNORTH();