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soc/intel/braswell/smbus.c: Add support for i2c mode block write

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Intel Braswell supports i2c block write using SMBus controller.

smbus_i2c_block_write() is added to configure SMBus controller in i2c
mode before calling do_i2c_block_write().

Add smbus.c to ramstage.

BUG=N/A
TEST=Verify LCD display is working on Facebook FBG-1701

Change-Id: I50c1a03f624b3ab3b987d4f3b1d15dac4374e48a
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33225
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This commit is contained in:
Frans Hendriks
2019-06-18 12:18:55 +02:00
committed by Martin Roth
parent e48be35bca
commit 863853cd2d
3 changed files with 59 additions and 0 deletions
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1
src/soc/intel/braswell/Makefile.inc
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@@ -35,6 +35,7 @@ ramstage-$(CONFIG_ELOG) += elog.c
ramstage-y += emmc.c ramstage-y += emmc.c
ramstage-y += gpio.c ramstage-y += gpio.c
ramstage-y += gfx.c ramstage-y += gfx.c
ramstage-y += smbus.c
ramstage-y += gpio_support.c ramstage-y += gpio_support.c
ramstage-y += iosf.c ramstage-y += iosf.c

26
src/soc/intel/braswell/include/soc/smbus.h Normal file
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@@ -0,0 +1,26 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2013 Google Inc.
* Copyright (C) 2015 Intel Corp.
* Copyright (C) 2019 Eltan B.V.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef _SOC_SMBUS_H_
#define _SOC_SMBUS_H_
/* PCI Configuration Space SMBus */
#define HOSTC 0x40
#define HOSTC_I2C_EN (1 << 2)
int smbus_i2c_block_write(u8 addr, u8 bytes, u8 *buf);
#endif /* _SOC_SMBUS_H_ */

32
src/soc/intel/braswell/smbus.c
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@@ -3,6 +3,7 @@
* *
* Copyright (C) 2017 Intel Corporation. * Copyright (C) 2017 Intel Corporation.
* Copyright (C) 2019 3mdeb * Copyright (C) 2019 3mdeb
* Copyright (C) 2019 Eltan B.V.
* *
* This program is free software; you can redistribute it and/or modify * This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by * it under the terms of the GNU General Public License as published by
@@ -16,6 +17,11 @@
#include <device/early_smbus.h> #include <device/early_smbus.h>
#include <soc/iomap.h> #include <soc/iomap.h>
#include <soc/pci_devs.h>
#include <device/pci_def.h>
#include <device/pci_type.h>
#include <device/pci_ops.h>
#include <soc/smbus.h>
#include <southbridge/intel/common/smbus.h> #include <southbridge/intel/common/smbus.h>
u8 smbus_read_byte(u32 smbus_dev, u8 addr, u8 offset) u8 smbus_read_byte(u32 smbus_dev, u8 addr, u8 offset)
@@ -27,3 +33,29 @@ u8 smbus_write_byte(u32 smbus_dev, u8 addr, u8 offset, u8 value)
{ {
return do_smbus_write_byte(SMBUS_BASE_ADDRESS, addr, offset, value); return do_smbus_write_byte(SMBUS_BASE_ADDRESS, addr, offset, value);
} }
int smbus_i2c_block_write(u8 addr, u8 bytes, u8 *buf)
{
#ifdef __SIMPLE_DEVICE__
pci_devfn_t dev = PCI_DEV(0, SMBUS_DEV, SMBUS_FUNC);
#else
struct device *dev = pcidev_on_root(SMBUS_DEV, SMBUS_FUNC);
#endif
u32 smbase;
u32 smb_ctrl_reg;
int status;
/* SMBus I/O BAR */
smbase = pci_read_config32(dev, PCI_BASE_ADDRESS_4) & 0xFFFFFFFE;
/* Enable I2C_EN bit in HOSTC register */
smb_ctrl_reg = pci_read_config32(dev, HOSTC);
pci_write_config32(dev, HOSTC, smb_ctrl_reg | HOSTC_I2C_EN);
status = do_i2c_block_write(smbase, addr, bytes, buf);
/* Restore I2C_EN bit */
pci_write_config32(dev, HOSTC, smb_ctrl_reg);
return status;
}