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cpu/intel/model_206ax: Lock MSR_PP_CURRENT_CONFIG

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Now that those registers are only written once set the lock bit to
protect it from runtime changes.

TEST: Lenovo X220 still boots.

Change-Id: I4c56a3cb322a0e75eb3dd366808068093928e10c
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78608
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This commit is contained in:
Patrick Rudolph
2023-10-20 14:37:07 +02:00
committed by Felix Held
parent ea04a53e69
commit 8685205ad1
2 changed files with 4 additions and 0 deletions
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2
src/cpu/intel/model_206ax/model_206ax.h
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@@ -73,8 +73,10 @@
#define PKG_POWER_LIMIT_TIME_MASK 0x7f #define PKG_POWER_LIMIT_TIME_MASK 0x7f
#define MSR_PP0_CURRENT_CONFIG 0x601 #define MSR_PP0_CURRENT_CONFIG 0x601
#define PP0_CURRENT_LIMIT_LOCK (1U << 31)
#define PP0_CURRENT_LIMIT (112 << 3) /* 112 A */ #define PP0_CURRENT_LIMIT (112 << 3) /* 112 A */
#define MSR_PP1_CURRENT_CONFIG 0x602 #define MSR_PP1_CURRENT_CONFIG 0x602
#define PP1_CURRENT_LIMIT_LOCK (1U << 31)
#define PP1_CURRENT_LIMIT_SNB (35 << 3) /* 35 A */ #define PP1_CURRENT_LIMIT_SNB (35 << 3) /* 35 A */
#define PP1_CURRENT_LIMIT_IVB (50 << 3) /* 50 A */ #define PP1_CURRENT_LIMIT_IVB (50 << 3) /* 50 A */
#define MSR_PKG_POWER_SKU_UNIT 0x606 #define MSR_PKG_POWER_SKU_UNIT 0x606

2
src/cpu/intel/model_206ax/model_206ax_init.c
View File

@@ -206,6 +206,7 @@ static void configure_c_states(void)
msr = rdmsr(MSR_PP0_CURRENT_CONFIG); msr = rdmsr(MSR_PP0_CURRENT_CONFIG);
msr.lo &= ~0x1fff; msr.lo &= ~0x1fff;
msr.lo |= PP0_CURRENT_LIMIT; msr.lo |= PP0_CURRENT_LIMIT;
msr.lo |= PP0_CURRENT_LIMIT_LOCK;
wrmsr(MSR_PP0_CURRENT_CONFIG, msr); wrmsr(MSR_PP0_CURRENT_CONFIG, msr);
/* Secondary Plane Current Limit */ /* Secondary Plane Current Limit */
@@ -215,6 +216,7 @@ static void configure_c_states(void)
msr.lo |= PP1_CURRENT_LIMIT_IVB; msr.lo |= PP1_CURRENT_LIMIT_IVB;
else else
msr.lo |= PP1_CURRENT_LIMIT_SNB; msr.lo |= PP1_CURRENT_LIMIT_SNB;
msr.lo |= PP1_CURRENT_LIMIT_LOCK;
wrmsr(MSR_PP1_CURRENT_CONFIG, msr); wrmsr(MSR_PP1_CURRENT_CONFIG, msr);
} }
} }