rockchip/rk3399: Move romstage.c to mainboard/gru
The romstage.c is more board related than soc specific, like setting the pwm regulators, so moving it to mainboard/gru. BRANCH=none BUG=chrome-os-partner:54819 TEST=Bootup on kevin board Change-Id: I83c6cde9f451480e47e2b4b549cedf65b345134c Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 35feeb07131a6a9de4adde035236987391833474 Original-Change-Id: If2bf245302eb4fb20bb089c1b3ffa03909722443 Original-Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/375398 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/16367 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Shunqian Zheng
committed by
Martin Roth
Martin Roth
parent
f706020ed6
commit
868cd71282
@@ -49,7 +49,6 @@ romstage-y += clock.c
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romstage-y += mmu_operations.c
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romstage-y += ../common/pwm.c
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romstage-y += timer.c
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romstage-y += romstage.c
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romstage-y += tsadc.c
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romstage-y += usb.c
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romstage-y += gpio.c
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@@ -1,133 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2016 Rockchip Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <arch/cache.h>
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#include <arch/cpu.h>
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#include <arch/exception.h>
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#include <arch/io.h>
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#include <arch/mmu.h>
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#include <boardid.h>
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#include <cbfs.h>
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#include <console/console.h>
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#include <delay.h>
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#include <program_loading.h>
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#include <romstage_handoff.h>
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#include <soc/addressmap.h>
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#include <soc/grf.h>
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#include <soc/mmu_operations.h>
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#include <soc/pwm.h>
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#include <soc/tsadc.h>
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#include <soc/sdram.h>
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#include <symbols.h>
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#include <soc/usb.h>
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static const uint64_t dram_size =
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(uint64_t)min((uint64_t)CONFIG_DRAM_SIZE_MB * MiB, MAX_DRAM_ADDRESS);
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static void init_dvs_outputs(void)
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{
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int duty_ns;
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uint32_t i;
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uint32_t id;
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write32(&rk3399_grf->iomux_pwm_0, IOMUX_PWM_0); /* GPU */
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write32(&rk3399_grf->iomux_pwm_1, IOMUX_PWM_1); /* Big */
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write32(&rk3399_pmugrf->iomux_pwm_2, IOMUX_PWM_2); /* Little */
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write32(&rk3399_pmugrf->iomux_pwm_3a, IOMUX_PWM_3_A); /* Centerlog */
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/*
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* Set up voltages for all DVS rails.
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*
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* LITTLE CPU: At the speed we're running at right now and on the
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* early silicon, .9V is sane. If/when we run faster, let's bump this.
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*
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* CENTER LOGIC: There are some claims that this should simply always
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* be .9 V. There are other claims that say that we need to adjust this
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* dynamically depending on the memory frequency. Until this is sorted
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* out, it appears that .9 V works for the 800 MHz.
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*
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* BIG CPU / GPU: These aren't used in coreboot. Init to .9V which is
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* supposed to be a good default.
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*
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* Details:
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* design_min = 0.8
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* design_max = 1.5
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* period = 3337 # 300 kHz
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* volt = 1.1
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* # Intentionally round down (higher volt) to be safe.
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* int((period / (design_max - design_min)) * (design_max - volt))
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*
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* Apparently a period of 3333 is determined by EEs to be ideal for our
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* board design / resistors / capacitors / regulators but due to
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* clock dividers we actually get 3337. Solving, we get:
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* period = 3337, volt = 1.1: 1906
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* period = 3337, volt = 1.0: 2383
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* period = 3337, volt = 0.9: 2860
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*/
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duty_ns = 2860; /* 0.9v */
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/* TODO: Clean all this up, implement proper pwm_regulator driver. */
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if (IS_ENABLED(CONFIG_BOARD_GOOGLE_KEVIN)) {
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id = board_id();
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if (id <= 2)
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duty_ns = 1906; /* 1.1v */
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else if (id == 3)
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duty_ns = 2621; /* 0.95v */
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else if (id >= 6) {
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/* GPU: 3337 * (12043 - 9000) / (12043 - 7984) = 2501 */
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pwm_init(0, 3337, 2501);
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/* BIG: 3337 * (12837 - 9000) / (12837 - 7985) = 2638 */
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pwm_init(1, 3337, 2638);
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/* LIT: 3337 * (12807 - 9000) / (12807 - 8009) = 2647 */
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pwm_init(2, 3337, 2647);
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/* CTR: 3337 * (10507 - 9500) / (10507 - 7996) = 1338 */
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pwm_init(3, 3337, 1338);
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return;
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}
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}
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for (i = 0; i < 4; i++)
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pwm_init(i, 3337, duty_ns);
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}
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static void prepare_usb(void)
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{
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/*
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* Do dwc3 core soft reset and phy reset. Kick these resets
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* off early so they get at least 100ms to settle.
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*/
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reset_usb_otg0();
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reset_usb_otg1();
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}
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void main(void)
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{
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console_init();
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tsadc_init(TSHUT_POL_HIGH);
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exception_init();
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/* Init DVS to conservative values. */
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init_dvs_outputs();
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prepare_usb();
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sdram_init(get_sdram_config());
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mmu_config_range((void *)0, (uintptr_t)dram_size, CACHED_MEM);
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mmu_config_range(_dma_coherent, _dma_coherent_size, UNCACHED_MEM);
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cbmem_initialize_empty();
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run_ramstage();
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}
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