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mb/google/guybrush: Enable guybrush variant

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Enable the building of guybrush variants and configure the first variant
also called guybrush.

BUG=b:180419462
TEST=builds

Signed-off-by: Mathew King <mathewk@chromium.org>
Change-Id: I3bed620378f9152277b4943ead1017f61a21ea82
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50845
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Mathew King
2021-02-17 09:57:36 -07:00
committed by Patrick Georgi
parent 5d47887965
commit 86a2324ee0
3 changed files with 16 additions and 0 deletions
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8
src/mainboard/google/guybrush/Kconfig
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@@ -38,10 +38,18 @@ config AMD_FWM_POSITION_INDEX
help help
TODO: might need to be adapted for better placement of files in cbfs TODO: might need to be adapted for better placement of files in cbfs
config VARIANT_DIR
string
default "guybrush" if BOARD_GOOGLE_GUYBRUSH
config DEVICETREE config DEVICETREE
string string
default "variants/baseboard/devicetree.cb" default "variants/baseboard/devicetree.cb"
config OVERRIDE_DEVICETREE
string
default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
config MAINBOARD_FAMILY config MAINBOARD_FAMILY
string string
default "Google_Guybrush" default "Google_Guybrush"

3
src/mainboard/google/guybrush/Makefile.inc
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@@ -6,4 +6,7 @@ ramstage-y += mainboard.c
ramstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c
subdirs-y += variants/baseboard subdirs-y += variants/baseboard
subdirs-y += variants/$(VARIANT_DIR)
CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include
CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include

5
src/mainboard/google/guybrush/variants/guybrush/overridetree.cb Normal file
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@@ -0,0 +1,5 @@
# SPDX-License-Identifier: GPL-2.0-or-later
chip soc/amd/cezanne
device domain 0 on
end # domain
end # chip soc/amd/cezanne