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soc/intel/mtl: Increase CAR_STACK_SIZE by 31KB for coreboot compatibility

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This change increases the DCACHE_BSP_STACK_SIZE from 512KB + 1KB to
512KB + 32KB, addressing a requirement specified by coreboot where
stack usage is higher than 1KB alone.

BUG=None
TEST=None

Change-Id: Iba3620b3b7c470176330f5e07989cd3f6238713e
Signed-off-by: Rishika Raj <rishikaraj@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83540
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
This commit is contained in:
Rishika Raj
2024-07-18 07:50:36 +00:00
committed by Subrata Banik
parent 8e48f94b39
commit 871f93549d
1 changed files with 2 additions and 2 deletions
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4
src/soc/intel/meteorlake/Kconfig
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@@ -171,12 +171,12 @@ config DCACHE_RAM_SIZE
config DCACHE_BSP_STACK_SIZE config DCACHE_BSP_STACK_SIZE
hex hex
default 0x80400 default 0x88000
help help
The amount of anticipated stack usage in CAR by bootblock and The amount of anticipated stack usage in CAR by bootblock and
other stages. In the case of FSP_USES_CB_STACK default value will be other stages. In the case of FSP_USES_CB_STACK default value will be
sum of FSP-M stack requirement(512KiB) and CB romstage stack requirement sum of FSP-M stack requirement(512KiB) and CB romstage stack requirement
(~1KiB). (~32KiB).
config FSP_TEMP_RAM_SIZE config FSP_TEMP_RAM_SIZE
hex hex