mb/google/octopus: I2C clock tuning for bloog

Tune I2C params for I2C buses 5, 6, and 7 to ensure that the
frequency does not exceed 400KHz.

BUG=b:131132499, b:128998988
BRANCH=octopus
TEST=emerge-octopus coreboot chromeos-bootimage and measured frequency
under 400 KHz

Change-Id: Ie8cfba72a0654402ccb0274c00b44fbfa2deea21
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32404
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>

src/mainboard/google/octopus/variants/bloog/overridetree.cb

@@ -49,12 +49,32 @@ chip soc/intel/apollolake
         #|                   | required to set up a BAR  |
         #|                   | for TPM communication     |
         #|                   | before memory is up       |
+        #| I2C5              | Audio                     |
+        #| I2C6              | Trackpad                  |
+        #| I2C7              | Touchscreen               |
         #+-------------------+---------------------------+
         register "common_soc_config" = "{
                 .gspi[0] = {
                         .speed_mhz = 1,
                         .early_init = 1,
                 },
+                .i2c[5] = {
+                        .speed = I2C_SPEED_FAST,
+                        .rise_time_ns = 104,
+                        .fall_time_ns = 52,
+                },
+                .i2c[6] = {
+                        .speed = I2C_SPEED_FAST,
+                        .rise_time_ns = 66,
+                        .fall_time_ns = 90,
+                        .data_hold_time_ns = 350,
+                },
+                .i2c[7] = {
+                        .speed = I2C_SPEED_FAST,
+                        .rise_time_ns = 44,
+                        .fall_time_ns = 90,
+                },
+
         }"
 
 	device domain 0 on