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AGESA fam15tn boards: Clean up devicetree

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Remove double nesting of chip northbridge/amd.
There is requirement to keep SPD address map in
the same chip block with device 0:18.2.

Change-Id: I67fcb59a63046865f660e628a61c2944b0f89a74
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30734
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: mikeb mikeb <mikebdp2@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Kyösti Mälkki
2019-01-08 09:32:44 +02:00
parent 4ebdf34e13
commit 872b42486a
5 changed files with 308 additions and 313 deletions
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85
src/mainboard/amd/parmer/devicetree.cb
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@@ -22,50 +22,49 @@ chip northbridge/amd/agesa/family15tn/root_complex
device domain 0 on
subsystemid 0x1022 0x1410 inherit
chip northbridge/amd/agesa/family15tn # CPU side of HT root complex
chip northbridge/amd/agesa/family15tn
device pci 0.0 on end # Root Complex
device pci 1.0 on end # Internal Graphics P2P bridge 0x99XX
device pci 1.1 on end # Internal Multimedia
device pci 2.0 on end # PCIE SLOT0 x16
device pci 3.0 off end
device pci 4.0 on end # PCIE MINI0
device pci 5.0 on end # PCIE MINI1
device pci 6.0 on end # PCIE Slot1 x1
device pci 7.0 on end # LAN
device pci 8.0 off end # NB/SB Link P2P bridge
end #chip northbridge/amd/agesa/family15tn
chip northbridge/amd/agesa/family15tn # PCI side of HT root complex
device pci 0.0 on end # Root Complex
device pci 1.0 on end # Internal Graphics P2P bridge 0x99XX
device pci 1.1 on end # Internal Multimedia
device pci 2.0 on end # PCIE SLOT0 x16
device pci 3.0 off end
device pci 4.0 on end # PCIE MINI0
device pci 5.0 on end # PCIE MINI1
device pci 6.0 on end # PCIE Slot1 x1
device pci 7.0 on end # LAN
device pci 8.0 off end # NB/SB Link P2P bridge
end #chip northbridge/amd/agesa/family15tn # PCI side of HT root complex
chip southbridge/amd/agesa/hudson # it is under NB/SB Link, but on the same pci bus
device pci 10.0 on end # XHCI HC0
device pci 10.1 on end # XHCI HC1
device pci 11.0 on end # SATA
device pci 12.0 on end # USB
device pci 12.2 on end # USB
device pci 13.0 on end # USB
device pci 13.2 on end # USB
device pci 14.0 on # SMBUS
chip drivers/generic/generic #dimm 0
device i2c 50 on end # 7-bit SPD address
end
chip drivers/generic/generic #dimm 1
device i2c 51 on end # 7-bit SPD address
end
end # SM
device pci 14.1 on end # IDE 0x439c
device pci 14.2 on end # HDA 0x4383
device pci 14.3 on end # LPC 0x439d
device pci 14.4 on end # PCI 0x4384 # PCI-b conflict with GPIO.
device pci 14.5 on end # USB 2
device pci 14.6 off end # Gec
device pci 14.7 on end # SD
device pci 15.0 off end # PCIe 0
device pci 15.1 off end # PCIe 1
device pci 15.2 off end # PCIe 2
device pci 15.3 off end # PCIe 3
end #chip southbridge/amd/agesa/hudson
chip southbridge/amd/agesa/hudson
device pci 10.0 on end # XHCI HC0
device pci 10.1 on end # XHCI HC1
device pci 11.0 on end # SATA
device pci 12.0 on end # USB
device pci 12.2 on end # USB
device pci 13.0 on end # USB
device pci 13.2 on end # USB
device pci 14.0 on # SMBUS
chip drivers/generic/generic #dimm 0
device i2c 50 on end # 7-bit SPD address
end
chip drivers/generic/generic #dimm 1
device i2c 51 on end # 7-bit SPD address
end
end # SM
device pci 14.1 on end # IDE 0x439c
device pci 14.2 on end # HDA 0x4383
device pci 14.3 on end # LPC 0x439d
device pci 14.4 on end # PCI 0x4384 # PCI-b conflict with GPIO.
device pci 14.5 on end # USB 2
device pci 14.6 off end # Gec
device pci 14.7 on end # SD
device pci 15.0 off end # PCIe 0
device pci 15.1 off end # PCIe 1
device pci 15.2 off end # PCIe 2
device pci 15.3 off end # PCIe 3
end #chip southbridge/amd/agesa/hudson
chip northbridge/amd/agesa/family15tn
device pci 18.0 on end
device pci 18.1 on end
device pci 18.2 on end
@@ -78,7 +77,7 @@ chip northbridge/amd/agesa/family15tn/root_complex
{ {0xA0, 0x00}, {0xA2, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses
{ {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses
}"
end
end #chip northbridge/amd/agesa/family15tn # CPU side of HT root complex
end #domain
end #chip northbridge/amd/agesa/family15tn/root_complex