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Revert "mb/google/brya/var/taeko: Fix PLD group order (W/A)"

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This revert commit acb17fec34a609c5b674ad0d2af04d47800530e2.

This issue was fixed in the OS, therefore the workaround can be
reverted.

BUG=b:210497855
BRANCH=firmware-brya-14505.B
TEST=build coreboot and boot into OS.

Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com>
Change-Id: Ic836e0cf53c2f9d30bd12851be285d864b2256b8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62565
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Kevin Chang 2022-03-03 21:08:26 +08:00 committed by Tim Wawrzynczak
parent e6fb29f2c0
commit 872c34a57f
1 changed files with 2 additions and 2 deletions
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4
src/mainboard/google/brya/variants/taeko/overridetree.cb
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@ -466,7 +466,7 @@ chip soc/intel/alderlake
register "desc" = ""USB3 Type-C Port C1 (DB)""
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
register "use_custom_pld" = "true"
register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))"
register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(3, 1))"
device ref tcss_usb3_port3 on
probe DB_USB DB_USB3_NO_A
probe DB_USB DB_USB3_1C_1A
@ -489,7 +489,7 @@ chip soc/intel/alderlake
register "desc" = ""USB2 Type-C Port C1 (DB)""
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
register "use_custom_pld" = "true"
register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))"
register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(3, 1))"
device ref usb2_port3 on
probe DB_USB DB_USB3_NO_A
probe DB_USB DB_USB3_1C_1A