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spd/lp5: Generate initial SPDs for Sabrina SoC

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Mainboards using Sabrina SoC will be using LP5 memory technology.
Generate the initial set of SPDs for the existing LP5 memory parts.

BUG=b:211510456
TEST=util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5

Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: Ibb43f26b36460290341c5ffcad1ef5a2ff1647c8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61543
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Karthikeyan Ramasubramanian
2022-02-01 22:29:57 -07:00
committed by Felix Held
parent fd07fa20da
commit 876cfe0ee2
6 changed files with 136 additions and 0 deletions
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32
spd/lp5/set-1/spd-empty.hex Normal file
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