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chromeec: Change the API for hostevent/wake masks to handle 64-bit

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ChromeEC is getting ready to bump up the hostevents and wake masks to
64-bits. The current commands to program hostevents/wake masks will
still operate on 32-bits only. A new EC host command will be added to
handle 64-bit hostevents/wake masks. In order to prevent individual
callers in coreboot from worrying about 32-bit/64-bit, the same API
provided by google/chromeec will be updated to accept 64-bit
parameters and return 64-bit values. Internally, host command handlers
will take care of masking these parameters/return values to
appropriate 32-bit/64-bit values.

BUG=b:69329196

Change-Id: If59f3f2b1a2aa5ce95883df3e72efc4a32de1190
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/22551
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Furquan Shaikh
2017-11-20 20:28:18 -08:00
committed by Furquan Shaikh
parent beb0468fce
commit 8788fd6395
10 changed files with 55 additions and 55 deletions
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8
src/ec/google/chromeec/smihandler.c
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@@ -57,7 +57,7 @@ static void clear_pending_events(void)
;
}
void chromeec_smi_sleep(int slp_type, uint32_t s3_mask, uint32_t s5_mask)
void chromeec_smi_sleep(int slp_type, uint64_t s3_mask, uint64_t s5_mask)
{
switch (slp_type) {
case ACPI_S3:
@@ -78,8 +78,8 @@ void chromeec_smi_sleep(int slp_type, uint32_t s3_mask, uint32_t s5_mask)
clear_pending_events();
}
void chromeec_smi_device_event_sleep(int slp_type, uint32_t s3_mask,
uint32_t s5_mask)
void chromeec_smi_device_event_sleep(int slp_type, uint64_t s3_mask,
uint64_t s5_mask)
{
switch (slp_type) {
case ACPI_S3:
@@ -96,7 +96,7 @@ void chromeec_smi_device_event_sleep(int slp_type, uint32_t s3_mask,
google_chromeec_get_device_current_events();
}
void chromeec_smi_apmc(int apmc, uint32_t sci_mask, uint32_t smi_mask)
void chromeec_smi_apmc(int apmc, uint64_t sci_mask, uint64_t smi_mask)
{
switch (apmc) {
case APM_CNT_ACPI_ENABLE: