soc/intel: Remove INTEL_CAR_NEM_ENHANCED_V2 config option
SF Mask MSRs' Programming which was done under this config selection will be moved under a new config option called CAR_HAS_SF_MASKS. This segregates the eNEM programming sequence based on sub features supported in each processor. Bug=b:171601324 BRANCH=volteer Test=Build volteer build and boot on Delbin EVT. Change-Id: If4d8d1ec52b7b79965fe1a957c48f571ec56dc63 Signed-off-by: Shreesh Chhabbi <shreesh.chhabbi@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48284 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
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Furquan Shaikh
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@@ -31,6 +31,8 @@ config CPU_SPECIFIC_OPTIONS
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select HAVE_FSP_GOP
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select HAVE_FSP_LOGO_SUPPORT
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select HAVE_INTEL_FSP_REPO
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select INTEL_CAR_NEM_ENHANCED
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select INTEL_DESCRIPTOR_MODE_CAPABLE
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select HAVE_SMI_HANDLER
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select INTEL_DESCRIPTOR_MODE_CAPABLE
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select INTEL_GMA_ACPI
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@@ -77,7 +79,6 @@ config CPU_SPECIFIC_OPTIONS
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select TSC_SYNC_MFENCE
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select UDELAY_TSC
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select UDK_2015_BINDING
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select USE_CAR_NEM_ENHANCED_V1
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config FSP_HYPERTHREADING
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bool "Enable Hyper-Threading"
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