soc/intel/{common, skylake}: Make ASPM enabling as common PCH feature

This patch moves required Kconfig selection for enabling ASPM feature
(like clk_pm, L1 state etc) from soc code  to intel common pch base code.

TEST=Run lspci -vvv | grep ASPM
The output shows the ASPM L1 is enable for pci devices

Change-Id: Ic77602a75f0c9ccf28ebfd57e53433dc90985a16
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/29653
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>

src/soc/intel/common/block/pcie/Kconfig

@@ -1,5 +1,9 @@
 config SOC_INTEL_COMMON_BLOCK_PCIE
 	bool
+	select PCIEXP_ASPM
+	select PCIEXP_CLK_PM
+	select PCIEXP_COMMON_CLOCK
+	select PCIEXP_L1_SUB_STATE
 	help
 	  Intel Processor common PCIE support
 

src/soc/intel/skylake/Kconfig

@@ -40,10 +40,6 @@ config CPU_SPECIFIC_OPTIONS
 	select NO_FIXED_XIP_ROM_SIZE
 	select PARALLEL_MP
 	select PARALLEL_MP_AP_WORK
-	select PCIEXP_ASPM
-	select PCIEXP_CLK_PM
-	select PCIEXP_COMMON_CLOCK
-	select PCIEXP_L1_SUB_STATE
 	select PCIEX_LENGTH_64MB
 	select REG_SCRIPT
 	select RTC