sravan/system76-coreboot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

soc/intel/{common, skylake}: Make ASPM enabling as common PCH feature

Browse Source 
This patch moves required Kconfig selection for enabling ASPM feature
(like clk_pm, L1 state etc) from soc code  to intel common pch base code.

TEST=Run lspci -vvv | grep ASPM
The output shows the ASPM L1 is enable for pci devices

Change-Id: Ic77602a75f0c9ccf28ebfd57e53433dc90985a16
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/29653
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit is contained in:
Subrata Banik 2018-11-19 16:23:01 +05:30 committed by Nico Huber
parent c1fa44091e
commit 87ca3898f9
2 changed files with 4 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
src/soc/intel/common/block/pcie/Kconfig
View File

@ -1,5 +1,9 @@
config SOC_INTEL_COMMON_BLOCK_PCIE config SOC_INTEL_COMMON_BLOCK_PCIE
bool bool
select PCIEXP_ASPM
select PCIEXP_CLK_PM
select PCIEXP_COMMON_CLOCK
select PCIEXP_L1_SUB_STATE
help help
Intel Processor common PCIE support Intel Processor common PCIE support

4
src/soc/intel/skylake/Kconfig
View File

@ -40,10 +40,6 @@ config CPU_SPECIFIC_OPTIONS
select NO_FIXED_XIP_ROM_SIZE select NO_FIXED_XIP_ROM_SIZE
select PARALLEL_MP select PARALLEL_MP
select PARALLEL_MP_AP_WORK select PARALLEL_MP_AP_WORK
select PCIEXP_ASPM
select PCIEXP_CLK_PM
select PCIEXP_COMMON_CLOCK
select PCIEXP_L1_SUB_STATE
select PCIEX_LENGTH_64MB select PCIEX_LENGTH_64MB
select REG_SCRIPT select REG_SCRIPT
select RTC select RTC