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soc/intel/quark: Enable Serial Port

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Add the code to enable debug serial output using HSUART1:

*  Enable the code using Kconfig value ENABLE_BUILTIN_HSUART1
*  Note that the BIST value is always zero as validated in
   esram_init.inc
*  The initial TSC value is currently not saved!

Testing on Galileo:
*  Edit the src/mainboard/intel/galileo/Makefile.inc file
   *  Add "select ADD_FSP_PDAT_FILE"
   *  Add "select ADD_FSP_RAW_BIN"
   *  Add "select ADD_RMU_FILE"
*  Place the FSP.bin file in the location specified by CONFIG_FSP_FILE
*  Place the pdat.bin files in the location specified by
   CONFIG_FSP_PDAT_FILE
*  Place the rmu.bin file in the location specified by CONFIG_RMU_FILE
*  Testing is successful if serial output is present on HSUART1 at
   115200 baud, 8-bit, no parity

Change-Id: I7e6181e8b9bc901c3ab236f0b56534850bb6bfd0
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13445
Tested-by: build bot (Jenkins)
Reviewed-by: FEI WANG <wangfei.jimei@gmail.com>
This commit is contained in:
Lee Leahy
2016-02-07 14:37:13 -08:00
committed by Martin Roth
parent 5d7df71cfe
commit 87df8d08d6
11 changed files with 316 additions and 1 deletions
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42
src/soc/intel/quark/Kconfig
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@@ -26,8 +26,37 @@ config CPU_SPECIFIC_OPTIONS
select ARCH_RAMSTAGE_X86_32
select ARCH_ROMSTAGE_X86_32
select ARCH_VERSTAGE_X86_32
select SOC_INTEL_COMMON
select TSC_CONSTANT_RATE
select UDELAY_TSC
select USE_MARCH_586
#####
# Debug serial output
# The following options configure the debug serial port
#####
config ENABLE_BUILTIN_HSUART1
bool "Enable built-in HSUART1"
default y
select NO_UART_ON_SUPERIO
select DRIVERS_UART_8250MEM_32
help
The Quark SoC has two HSUART. Choose this option to configure the pads
and enable HSUART1, which can be used for the debug console.
config TTYS0_BASE
hex "HSUART1 Base Address"
depends on ENABLE_BUILTIN_HSUART1
default 0xA0019000
help
Memory mapped MMIO of HSUART1.
config TTYS0_LCS
int
depends on ENABLE_BUILTIN_HSUART1
default 3
#####
# Debug support
# The following options provide debug support for the Quark coreboot
@@ -64,6 +93,19 @@ config ENABLE_DEBUG_LED_TEMPRAMINIT
help
Indicate that TempRamInit was successful.
#####
# ESRAM layout
# Specify the portion of the ESRAM for coreboot to use as its data area.
#####
config DCACHE_RAM_BASE
hex
default 0x80070000
config DCACHE_RAM_SIZE
hex
default 0x00008000
#####
# Flash layout
# Specify the size of the coreboot file system in the read-only