From 87e186e7a8be5e2e8f42781b417ef6b36f0f64e8 Mon Sep 17 00:00:00 2001 From: Jeremy Soller Date: Thu, 20 Jun 2019 15:58:29 -0600 Subject: [PATCH] Update gpe config --- src/mainboard/system76/cfl-h/devicetree.cb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/system76/cfl-h/devicetree.cb b/src/mainboard/system76/cfl-h/devicetree.cb index 2f7dd690e6..2ff01fdd03 100644 --- a/src/mainboard/system76/cfl-h/devicetree.cb +++ b/src/mainboard/system76/cfl-h/devicetree.cb @@ -177,7 +177,7 @@ chip soc/intel/cannonlake # offset bits also need to be changed. # sudo devmem2 0xfe001920 (pmc_bar + GPIO_GPE_CFG) register "gpe0_dw0" = "PMC_GPP_K" - register "gpe0_dw1" = "PMC_GPP_D" + register "gpe0_dw1" = "PMC_GPP_G" register "gpe0_dw2" = "PMC_GPP_E" # Actual device tree