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mb/google/mancomb: Enable Chrome EC

Browse Source 
BUG=b:182211161
TEST=builds

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Id1617be67bfc5d2f142358ae8a70c3e575a94c6d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51489
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
This commit is contained in:
Eric Lai
2021-03-15 11:19:01 +08:00
committed by Raul Rangel
parent b95f848766
commit 87e27e1d0e
6 changed files with 87 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
src/mainboard/google/mancomb/Kconfig
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@@ -9,14 +9,14 @@ config BOARD_SPECIFIC_OPTIONS
def_bool y
select AMD_SOC_CONSOLE_UART
select BOARD_ROMSIZE_KB_16384
select EC_GOOGLE_CHROMEEC
select EC_GOOGLE_CHROMEEC_ESPI
select HAVE_ACPI_RESUME
select MAINBOARD_HAS_CHROMEOS
select SOC_AMD_CEZANNE
select SOC_AMD_COMMON_BLOCK_USE_ESPI
config CHROMEOS
select EC_GOOGLE_CHROMEEC
select EC_GOOGLE_CHROMEEC_ESPI
select EC_GOOGLE_CHROMEEC_SWITCHES
config VBOOT

1
src/mainboard/google/mancomb/Makefile.inc
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@@ -4,6 +4,7 @@ bootblock-y += bootblock.c
verstage-y += verstage.c
ramstage-y += ec.c
ramstage-y += mainboard.c
ramstage-$(CONFIG_CHROMEOS) += chromeos.c

20
src/mainboard/google/mancomb/ec.c Normal file
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@@ -0,0 +1,20 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
#include <acpi/acpi.h>
#include <amdblocks/gpio_banks.h>
#include <amdblocks/smi.h>
#include <ec/google/chromeec/ec.h>
#include <variant/ec.h>
void mainboard_ec_init(void)
{
const struct google_chromeec_event_info info = {
.log_events = MAINBOARD_EC_LOG_EVENTS,
.sci_events = MAINBOARD_EC_SCI_EVENTS,
.s3_wake_events = MAINBOARD_EC_S3_WAKE_EVENTS,
.s5_wake_events = MAINBOARD_EC_S5_WAKE_EVENTS,
.s0ix_wake_events = MAINBOARD_EC_S0IX_WAKE_EVENTS,
};
google_chromeec_events_init(&info, acpi_is_wakeup_s3());
}

2
src/mainboard/google/mancomb/mainboard.c
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@@ -2,6 +2,7 @@
#include <baseboard/variants.h>
#include <device/device.h>
#include <variant/ec.h>
#include <vendorcode/google/chromeos/chromeos.h>
static void mainboard_configure_gpios(void)
@@ -17,6 +18,7 @@ static void mainboard_configure_gpios(void)
static void mainboard_init(void *chip_info)
{
mainboard_configure_gpios();
mainboard_ec_init();
}
static void mainboard_enable(struct device *dev)

59
src/mainboard/google/mancomb/variants/baseboard/include/baseboard/ec.h Normal file
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@@ -0,0 +1,59 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
#ifndef __MAINBOARD_EC_H__
#define __MAINBOARD_EC_H__
#include <ec/ec.h>
#include <ec/google/chromeec/ec_commands.h>
#include <baseboard/gpio.h>
#include <soc/gpio.h>
#define MAINBOARD_EC_SCI_EVENTS \
(EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) \
| EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) \
| EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) \
| EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) \
| EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) \
| EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU) \
| EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE) \
| EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_MUX))
#define MAINBOARD_EC_SMI_EVENTS (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED))
/* EC can wake from S5 with power button */
#define MAINBOARD_EC_S5_WAKE_EVENTS EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON)
/* EC can wake from S3 with lid, power button or mode change event */
#define MAINBOARD_EC_S3_WAKE_EVENTS \
(MAINBOARD_EC_S5_WAKE_EVENTS | EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) \
| EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) \
| EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED) \
| EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE))
#define MAINBOARD_EC_S0IX_WAKE_EVENTS (MAINBOARD_EC_S3_WAKE_EVENTS)
/* Log EC wake events plus EC shutdown events */
#define MAINBOARD_EC_LOG_EVENTS \
(EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) \
| EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC))
/*
* ACPI related definitions for ASL code.
*/
/* Set GPI for SCI */
#define EC_SCI_GPI GEVENT_24 /* eSPI system event -> GPE 24 */
#define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */
#define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */
/* Enable EC sync interrupt */
#define EC_ENABLE_SYNC_IRQ_GPIO
/* EC sync irq */
#define EC_SYNC_IRQ GPIO_84
/* Enable EC backed PD MCU device in ACPI */
#define EC_ENABLE_PD_MCU_DEVICE
#endif /* __MAINBOARD_EC_H__ */

3
src/mainboard/google/mancomb/variants/mancomb/include/variant/ec.h Normal file
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@@ -0,0 +1,3 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
#include <baseboard/ec.h>