soc/intel/adl: Disable FSP debug output if !FSP_ENABLE_SERIAL_DEBUG
This patch binds all FSP-M and FSP-S UPDs required for serial redirection with `FSP_ENABLE_SERIAL_DEBUG` config to allow coreboot to choose when to enable FSP debug output redirection to serial port. For example: PcdSerialDebugLevel => For controlling FSP debug level between FSP-M/S SerialDebugMrcLevel => For controllig MRC debug level. With this change FSP debug output will only be enabled when the user enables `FSP_ENABLE_SERIAL_DEBUG` from site-local config with coreboot serial image. BUG=b:225544587 TEST=Able to build and boot brya. Also, the FSP debug log is exactly the same before and with this code change. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I779c56b8b0fdebf45ea85b3b456a2d8066e26489 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63167 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@@ -511,8 +511,10 @@ static void fill_fsps_xdci_params(FSP_S_CONFIG *s_cfg,
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static void fill_fsps_uart_params(FSP_S_CONFIG *s_cfg,
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const struct soc_intel_alderlake_config *config)
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{
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if (CONFIG(FSP_USES_CB_DEBUG_EVENT_HANDLER))
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s_cfg->FspEventHandler = (UINT32)((FSP_EVENT_HANDLER *)fsp_debug_event_handler);
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if (CONFIG(FSP_USES_CB_DEBUG_EVENT_HANDLER) && CONFIG(CONSOLE_SERIAL) &&
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CONFIG(FSP_ENABLE_SERIAL_DEBUG))
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s_cfg->FspEventHandler = (UINT32)((FSP_EVENT_HANDLER *)
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fsp_debug_event_handler);
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/* PCH UART selection for FSP Debug */
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s_cfg->SerialIoDebugUartNumber = CONFIG_UART_FOR_CONSOLE;
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ASSERT(ARRAY_SIZE(s_cfg->SerialIoUartAutoFlow) > CONFIG_UART_FOR_CONSOLE);
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