nb/intel/sandybridge: Add a bunch of MCHBAR defines

While we are at it, also:
- Rename related variables to match the register names.
- Update some comments to better reflect what some registers are about.
- Add various FIXME comments on registers that seem to be used wrongly.

With BUILD_TIMELESS=1, this commit does not change the coreboot build of:
- Asus P8H61-M PRO with native raminit.
- Gigabyte GA-H61MA-D3V with native raminit.
- Lenovo Thinkpad X230 with native raminit.
- Lenovo Thinkpad X220 with MRC raminit.

Change-Id: I5e5fe56eaa90842dbbdd1bfbbcb7709237b4c486
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38036
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This commit is contained in:
Angel Pons
2020-01-05 20:21:20 +01:00
committed by Felix Held
parent d589be3648
commit 8852188113
10 changed files with 1065 additions and 732 deletions

View File

@ -293,7 +293,7 @@ static void init_dram_ddr3(int min_tck, int s3resume)
int err;
u32 cpu;
MCHBAR32(0x5f00) |= 1;
MCHBAR32(SAPMCTL) |= 1;
/* Wait for ME to be ready */
intel_early_me_init();
@ -404,12 +404,12 @@ static void init_dram_ddr3(int min_tck, int s3resume)
if (err)
die("raminit failed");
/* FIXME: should be hardware revision-dependent. */
MCHBAR32(0x5024) = 0x00a030ce;
/* FIXME: should be hardware revision-dependent. The register only exists on IVB. */
MCHBAR32(CHANNEL_HASH) = 0x00a030ce;
set_scrambling_seed(&ctrl);
set_42a0(&ctrl);
set_normal_operation(&ctrl);
final_registers(&ctrl);